公开(公告)号：US20240397226A1

公开(公告)日：2024-11-28

申请号：US18322431

申请日：2023-05-23

Applicant: OMNIVISION TECHNOLOGIES, INC.

Inventor： Jiayu Guo ,  Hiroaki Ebihara ,  Liang Zuo ,  Lihang Fan ,  Satoshi Sakurai

IPC: H04N25/77 ,  G06F7/02 ,  G06F7/57

Abstract: An arithmetic logic unit (ALU) includes a front end latch stage coupled to a Gray code (GC) generator to latch GC outputs, a signal latch stage coupled to latch outputs of the front end latch stage, a GC to binary stage coupled to generate a binary representation of the GC outputs, an adder stage including first inputs coupled to receive outputs of the GC to binary stage, a pre-latch stage coupled to latch outputs of the adder stage, and a feedback latch stage coupled to latch outputs of the pre-latch stage in response to a feedback latch enable signal. The feedback latch enable signal is one of a correlated multiple sampling (CMS) feedback enable signal and a non-CMS feedback enable signal. The ALU is configured to perform CMS calculations in response to the CMS feedback enable signal and perform non-CMS calculations in response to the non-CMS feedback enable signal.

公开(公告)号：US10659055B1

公开(公告)日：2020-05-19

申请号：US16190862

申请日：2018-11-14

Applicant: OmniVision Technologies, Inc.

Inventor： Satoshi Sakurai ,  Hiroaki Ebihara

IPC: H03K23/00 ,  H03M1/12 ,  H04N5/357 ,  H04N5/378 ,  H03M1/56

Abstract: An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M-L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.

公开(公告)号：US20200153440A1

公开(公告)日：2020-05-14

申请号：US16190862

申请日：2018-11-14

Applicant: OmniVision Technologies, Inc.

Inventor： Satoshi Sakurai ,  Hiroaki Ebihara

IPC: H03K23/00 ,  H03M1/12 ,  H03M1/56 ,  H04N5/378 ,  H04N5/357

Abstract: An N bit counter includes a lower counter having a first output having M bits that operates a first counting frequency. An upper counter having a second output having N−M+L bits operates a second counting frequency. The second counting frequency is equal to the first counting frequency divided by 2(M−L). An error correction controller is coupled to receive the first and second outputs and perform operations that include comparing the L least significant bits (LSBs) of the second output and at least one most significant bit (MSB) of the first output, and correcting the N−M MSBs of the second output in response to the comparison. The lower bits of the N bit counter are the M bits of the first output, and the upper bits of the N bit counter are the corrected N−M MSBs of the second output.