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公开(公告)号：US12126365B2
公开(公告)日：2024-10-22
申请号：US18052425
申请日：2022-11-03
Applicant: NXP B.V.
Inventor： Victor Pecanins Martinez , Robert van Veldhoven
IPC: H03M3/00
Abstract: A continuous-time delta-sigma modulator, CTDSM (400, 500, 700, 800) is described that comprises: an operational transconductance amplifier, OTA, (406, 506, 706, 806) having an input port (404, 504, 719, 739, 819, 839) configured to receive an analog input signal and an output port (408, 508, 707, 708, 807, 808); an input low pass filter network comprising at least one input resistor, R1, (402, 502, 702, 722, 802, 822) at least one first shunt capacitor, C1, (403, 503, 703, 803) and at least one feedback resistor, Rdac (410, 510, 710, 810, 730, 830) connected to the input port of the OTA; an output filter network comprising a shunt second resistor, R2, (415, 515, 715, 815) in parallel to a second shunt capacitor, C2, (414, 514, 714, 814), and coupled to the output port (408, 508, 707, 708, 807, 808) of the OTA; a quantizer (413, 513, 713, 813) connected to the output filter network and having at least one output connected to the input port of the OTA via the at least one feedback resistor, Rdac; and wherein the input and output port of the OTA connected by a third feedforward-feedback capacitor, C3, (409, 509, 709, 729, 809, 829) arranged to provide a positive feedback around the OTA.
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公开(公告)号：US11962331B2
公开(公告)日：2024-04-16
申请号：US17814978
申请日：2022-07-26
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
IPC: H03M3/00
Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.
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公开(公告)号：US20230421172A1
公开(公告)日：2023-12-28
申请号：US17822951
申请日：2022-08-29
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
Abstract: An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.
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公开(公告)号：US20230238981A1
公开(公告)日：2023-07-27
申请号：US17648584
申请日：2022-01-21
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
IPC: H03M3/00
CPC classification number: H03M3/344
Abstract: Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.
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公开(公告)号：US12184308B2
公开(公告)日：2024-12-31
申请号：US17822951
申请日：2022-08-29
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
Abstract: An interface circuit includes an analogue to digital converter having an input configured to receive an input signal having an unknown DC bias voltage via an input resistance and provide an output signal to an ADC feedback loop. The ADC feedback loop includes a digital filter arranged to digitally filter the fedback output signal. A digital to analogue converter (DAC) forming a DC feedback loop with the ADC and arranged to convert the digitally filtered fedback output signal to an analogue signal that is provided to the input of the ADC, wherein the analogue signal that is provided to the input of the ADC is arranged to include a DC bias component that is comparable to a DC bias component of a current of the input signal passing through the input resistor.
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Patent Agency Ranking
公开(公告)号：US20240380413A1
公开(公告)日：2024-11-14
申请号：US18313414
申请日：2023-05-08
Applicant: NXP B.V.
IPC: H03M3/00
Abstract: An analog to digital circuit that includes a feedback circuit with a return to open (RTO), digital to analog converter (DAC) that provides an analog signal that is indicative of an output of an ADC component of the ADC. During a data phase, the output of the DAC is provided to a combiner input through a resistive circuit. The combiner also receives an analog input signal at another input and provides a combined output signal to the ADC component. During a reset phase, the output of the DAC is provided to the combiner through a lower resistance bypass circuit to bypass the resistive circuit.
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公开(公告)号：US11722146B1
公开(公告)日：2023-08-08
申请号：US17648584
申请日：2022-01-21
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
IPC: H03M3/00
CPC classification number: H03M3/344
Abstract: Systems and methods for correction of sigma-delta analog-to-digital converters (ADCs) using neural networks are described. In an illustrative, non-limiting embodiment, a device may include: an ADC; a filter coupled to the ADC, where the filter is configured to receive an output from the ADC and to produce a filtered output; and a neural network coupled to the filter, where the neural network is configured to receive the filtered output and to produce a corrected output.
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公开(公告)号：US11695377B2
公开(公告)日：2023-07-04
申请号：US17501757
申请日：2021-10-14
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , John Pigott
CPC classification number: H03F3/387 , H03F3/1935 , H03F3/45179 , H03F3/45183
Abstract: An amplifier including a P-channel transistor having current terminals coupled between a first node and a second node and having a control terminal coupled to a third node receiving an input voltage, an N-channel transistor having current terminals coupled between a fourth node developing an output voltage and a supply voltage reference and having a control terminal coupled to the second node, a first resistor coupled between the first node and a supply voltage, a second resistor coupled between the first and fourth nodes, and a current sink sinking current from the second node to the supply reference node. The amplifier may be converted to differential form for amplifying a differential input voltage. Current devices may be adjusted for common mode, and may be moved or added to improve headroom or to improve power supply rejection. Chopper circuits may be added to reduce 1/f noise.
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公开(公告)号：US11658620B2
公开(公告)日：2023-05-23
申请号：US17459050
申请日：2021-08-27
Applicant: NXP B.V.
Inventor： Robert van Veldhoven , Khalid Mabtoul , Dmitrij Andreevits Sjwed
IPC: H03F3/181
CPC classification number: H03F3/181 , H03F2200/03 , H03F2200/264
Abstract: A digital signal generator apparatus and method is described. The digital signal generator includes a counter, an integrator and a comparator. The counter counts up or down from an initial counter value dependent on a counter control input. The comparator has a first input coupled to the counter output, a threshold input and a comparator output coupled to the counter control input. The integrator has an input coupled to the counter output and an output coupled to the digital signal generator output. The digital signal generator determines the count direction after the initial direction dependent on the comparison between a threshold value applied to the threshold input and the counter output value. The digital signal generator may implement the generation of a waveform having an approximation to a raised cosine function. The generated waveform may be used for audio artefact reduction in an audio amplifier during mute or unmute operations or during power up power down operations.
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公开(公告)号：US20230038361A1
公开(公告)日：2023-02-09
申请号：US17814978
申请日：2022-07-26
Applicant: NXP B.V.
Inventor： Robert van Veldhoven
IPC: H03M3/00
Abstract: A sigma-delta ADC is described including a passive filter with an input coupled to the ADC input and a filter output. A gain stage has an input connected to the filter output. A quantiser has an input connected to the gain stage output and a quantiser output. The passive filter includes a first filter resistor between the filter input and the filter output and a filter capacitor having first terminal coupled to the filter output. A feedback resistor is coupled between the quantiser output and the filter output and receives a negative of the value of the output to provide negative feedback to the filter output. The gain stage has a capacitor and resistor in series, and a gain element connected to the gain stage input and an output connected to the gain stage output. One terminal of the gain stage capacitor is connected to the gain element output.
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