公开(公告)号：US12205942B2

公开(公告)日：2025-01-21

申请号：US17374214

申请日：2021-07-13

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax ,  Dongyong Zhu ,  Feng Cong ,  Tingting Pan

IPC: H01L27/02

Abstract: An integrated circuit includes two N wells from two different devices in close proximity to each other with each N well biased by two different terminals. The N wells are at least partially surrounded by P type regions that are biased by a terminal. The integrated circuit includes conductivity reduction features that increase the resistivity of current paths to a P type regions of one device on a side closest the other device. The integrated circuit includes two conductive tie biasing structures each located directly over an N type region of the substrate and directly over a P type region of the substrate. The two conductive tie biasing structures are not electrically connected to each other and are not electrically coupled to each other by a conductive biasing structure.

公开(公告)号：US20230317726A1

公开(公告)日：2023-10-05

申请号：US17657894

申请日：2022-04-04

Applicant: NXP B.V.

Inventor： Guido Wouter Willem Quax

IPC: H01L27/092 ,  H01L27/02 ,  H01L27/07

CPC classification number: H01L27/0921 ,  H01L27/0727 ,  H01L27/0255

Abstract: An integrated circuit includes a first semiconductor device with an N type region biased by a first terminal and a second semiconductor device with a second region. An N type guard region is located laterally between the N type region of the first semiconductor device and the second region. A P type region is isolated in the N type guard region and is biased by a second terminal. The N type guard region is either electrically coupled to the second terminal through a resistor circuit or is characterized as floating.

公开(公告)号：US10938203B2

公开(公告)日：2021-03-02

申请号：US16173898

申请日：2018-10-29

Applicant: NXP B.V.

Inventor： Anu Mathew ,  Guido Wouter Willem Quax

IPC: H02H9/04

Abstract: One example discloses a voltage limiting device, including: a first I/O port; a second I/O port; a voltage limiter, coupled to the first and second I/O ports, and configured to shunt a voltage received on the first and/or second I/O ports having an absolute value greater than a voltage limit; wherein the voltage limiter includes a first portion and a second portion; wherein the first portion includes a first current shunt coupled between the first I/O port and a mid-net, and a second current shunt coupled between the second I/O port and the mid-net; and wherein the second portion includes a third current shunt having one end coupled to the mid-net and another end coupled to a ground.

公开(公告)号：US20160372921A1

公开(公告)日：2016-12-22

申请号：US15172208

申请日：2016-06-03

Applicant: NXP B.V.

Inventor： Da-Wei Lai ,  Guido Wouter Willem Quax ,  Gijs Jan De Raad

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0262 ,  H01L27/0266 ,  H01L27/0285

Abstract: An electrostatic discharge power rail clamp circuit and an integrated circuit including the same. The power rail clamp circuit includes a first power rail, a second power rail and a first node. The circuit further includes an n-channel field effect transistor having a source and drain located in an isolated p-well in a semiconductor substrate. The drain is connected to the first power rail. The source and isolated p-well are connected to the first node. The circuit also includes a capacitor connected between the first node and the second power rail. The circuit further includes a resistor connected between the first power rail and the first node. The circuit also includes an inverter for controlling the gate of the field effect transistor, wherein the inverter has an input connected to the first node. The circuit further a silicon controlled rectifier connected between the first node and the second power rail.

Abstract translation: 一种静电放电电力轨钳位电路及包括该电路的集成电路。 电力轨道钳位电路包括第一电力轨道，第二电力轨道和第一节点。 该电路还包括n沟道场效应晶体管，其源极和漏极位于半导体衬底中的隔离p阱中。 漏极连接到第一个电源轨。 源和隔离p阱连接到第一个节点。 电路还包括连接在第一节点和第二电力轨道之间的电容器。 电路还包括连接在第一电源轨和第一节点之间的电阻器。 电路还包括用于控制场效应晶体管的栅极的反相器，其中反相器具有连接到第一节点的输入端。 电路还包括连接在第一节点和第二电力轨道之间的可控硅整流器。