公开(公告)号：US10825794B2

公开(公告)日：2020-11-03

申请号：US16119572

申请日：2018-08-31

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00 ,  H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/324 ,  H01L21/306

Abstract: The present disclosure is directed to method for preparing a semiconductor apparatus having a plurality of bonded semiconductor devices formed by a fusion bonding technique. The method includes operations of forming a first semiconductor device having a first conductive portion, a first dielectric portion adjacent to the first conductive portion, and a depression at an upper surface of the first conductive portion; forming a second semiconductor device having a second conductive portion and a second dielectric portion adjacent to the second conductive portion; disposing the first semiconductor device and the second semiconductor device in a manner such that the first conductive portion faces the second conductive portion; and expanding at least one of the first conductive portion and the second conductive portion to fill the depression.

公开(公告)号：US10290512B2

公开(公告)日：2019-05-14

申请号：US15598304

申请日：2017-05-17

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/00 ,  H01L23/482 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate and a first conductive bump. The semiconductor substrate has an integrated circuit and an interconnection metal layer, and a tilt surface is formed on an edge of the semiconductor substrate. The first conductive bump is electrically connected to the integrated circuit via the interconnection metal layer, and is disposed on the tilt surface, wherein a profile of the first conductive bump extends beyond a side surface of the edge of the semiconductor layer.

公开(公告)号：US10256179B2

公开(公告)日：2019-04-09

申请号：US15424898

申请日：2017-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/56 ,  H01L23/31

Abstract: A package structure includes an interconnection layer; a passivation layer disposed on the interconnection layer, in which the interconnection layer and the passivation layer defined at least one opening; at least one elastic bump disposed on the interconnection layer, in which a portion of the elastic bump is embedded in the opening; and a conductive layer disposed on the elastic bump.

公开(公告)号：US10192853B2

公开(公告)日：2019-01-29

申请号：US15853456

申请日：2017-12-22

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/498 ,  H01L23/00 ,  H01L23/48

Abstract: The present disclosure provides a method for preparing a semiconductor apparatus. The semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

公开(公告)号：US10170432B2

公开(公告)日：2019-01-01

申请号：US15493119

申请日：2017-04-20

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/552 ,  H01L23/522 ,  H01L23/532 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure is used to be electrically connected to a power terminal or a ground terminal.

公开(公告)号：US09966363B1

公开(公告)日：2018-05-08

申请号：US15423973

申请日：2017-02-03

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/481 ,  H01L23/49838 ,  H01L24/05 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17181 ,  H01L2224/81191 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788

Abstract: A semiconductor apparatus includes a first semiconductor die and a second semiconductor die stacked onto the first semiconductor die in a horizontally shifted manner. The first semiconductor die includes a first chip selection terminal and a first lower terminal electrically connected to the first chip selection terminal. The second semiconductor die includes a second chip selection terminal electrically connected to a first upper terminal of the first semiconductor die via a second lower terminal of the second semiconductor die. The first upper terminal which is electrically connected to the second chip selection terminal is not electrically connected to the first lower terminal which is electrically connected to the first chip selection terminal.

公开(公告)号：US09881867B1

公开(公告)日：2018-01-30

申请号：US15409551

申请日：2017-01-19

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/481 ,  H01L21/7682 ,  H01L21/76831

Abstract: A conductive connection structure includes a semiconductor substrate, a conductive pillar, and a stress buffer layer. The conductive pillar is in the semiconductor substrate. The stress buffer layer is between the semiconductor substrate and the conductive pillar. The conductive pillar has a protruding portion penetrating through the stress buffer layer.

公开(公告)号：US10566294B2

公开(公告)日：2020-02-18

申请号：US16202113

申请日：2018-11-28

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin ,  Chin-Lung Chu

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, at least one semiconductor device, a through-substrate via (TSV), and a shield structure. The substrate has a front side surface and a back side surface. The semiconductor device is disposed on the front side surface. The TSV is disposed in the substrate. The TSV is exposed by the front side surface and the back side surface, and the TSV is electrically connected to the semiconductor device. The shield structure is disposed in the substrate and surrounds the TSV. The shield structure is exposed by the front side surface, the shield structure is electrically isolated from the TSV, and the shield structure and the TSV have bottom ends at the same height.

公开(公告)号：US10535621B2

公开(公告)日：2020-01-14

申请号：US16185804

申请日：2018-11-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L23/31 ,  H01L25/065 ,  H01L23/00 ,  H01L21/56

Abstract: The present disclosure provides a method for preparing a semiconductor package. The method includes providing a first device having a first upper surface and a first side, wherein the first upper surface and the first side form a first corner. The method also includes forming a bump structure over the first upper surface, wherein the bump structure extends laterally across the first side of the first device.

公开(公告)号：US10361171B2

公开(公告)日：2019-07-23

申请号：US15859703

申请日：2018-01-01

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Po-Chun Lin

IPC: H01L25/065 ,  H01L21/683 ,  H01L23/31 ,  H01L25/00

Abstract: A stacked package structure includes a first package structure having a first surface and a second surface opposite to the first surface. The first package structure includes a least one first die having a first active region disposed at a bottom of the first die; a first redistribution layer disposed on the top surface of the first die; and a plurality of first bumps disposed on the bottom surface of the first active region.