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公开(公告)号:US20230395324A1
公开(公告)日:2023-12-07
申请号:US18237505
申请日:2023-08-24
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yoshiyuki ABE , Kazuhisa UCHIDA
CPC classification number: H01G4/1227 , H01G4/0085 , H01G4/2325 , H01G4/30
Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
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公开(公告)号:US20220262568A1
公开(公告)日:2022-08-18
申请号:US17591628
申请日:2022-02-03
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Yoshiyuki ABE , Kazuhisa UCHIDA
Abstract: A multilayer ceramic capacitor includes first dielectric ceramic layers each with a thickness of about 0.48 μm or more and about 0.50 μm or less in the lamination direction, and additional dielectric ceramic layers each with a thickness of about 10 μm or more and about 15 μm or less in the width direction. A number of dielectric particles in each first dielectric ceramic layer in a thickness direction is three or more and six or less. A number of dielectric particles in each additional dielectric ceramic layer in a thickness direction is 100 or more and 150 or less. When the number of dielectric particles in each of first dielectric ceramic layer is NT, and the number of dielectric particles in each additional dielectric ceramic layer is NW, a ratio of NT to NW is about 1:23.08 or more and about 1:46.15 or less.
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公开(公告)号:US20200312569A1
公开(公告)日:2020-10-01
申请号:US16822070
申请日:2020-03-18
Applicant: Murata Manufacturing Co., Ltd.
Inventor: Kazuhisa UCHIDA
Abstract: A multilayer ceramic capacitor includes a laminate including a dielectric ceramic layer and first and second internal electrode layers laminated in a lamination direction, and first and second external electrode connected to the internal electrode layers. The laminate includes a central layer portion, a peripheral layer portion sandwiching the central layer portion, and a side margin sandwiching the central layer portion and the peripheral layer portion. The side margin includes an inner layer and an outer layer. In a cross section including a lamination direction and a width direction obtained by cutting the laminate at the center in a longitudinal direction of the laminate, the ceramic grains in the dielectric ceramic layer between ends of the internal electrode layers in the width direction have a smaller diameter than the ceramic grains in the dielectric ceramic layer at the center of the central layer portion in the width direction.
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