公开(公告)号：US20160372431A1

公开(公告)日：2016-12-22

申请号：US15250888

申请日：2016-08-29

Applicant: MEDIATEK INC.

Inventor： Chun-Liang Chen ,  Tien-Chang Chang ,  Chien-Chih Lin

IPC: H01L23/00

CPC classification number: H01L23/5286 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5283 ,  H01L24/05 ,  H01L27/088 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05085 ,  H01L2224/05096 ,  H01L2224/05124 ,  H01L2224/05624 ,  H01L2924/00014

Abstract: The present invention provides a semiconductor device. The semiconductor device comprises: a metal pad and a first specific metal layer routing and a second specific metal layer routing. The metal pad is positioned on a first metal layer of the semiconductor device. The first specific metal layer routing and the second specific metal layer routing are formed in a second metal layer of the semiconductor device, wherein the first specific metal layer routing is directly under the metal pad and the second specific metal layer routing is not directly positioned under the metal pad.

Abstract translation: 本发明提供一种半导体器件。 半导体器件包括：金属焊盘和第一特定金属层布线和第二特定金属层布线。 金属焊盘位于半导体器件的第一金属层上。 第一特定金属层布线和第二特定金属层布线形成在半导体器件的第二金属层中，其中第一特定金属层布线直接在金属焊盘下方，并且第二特定金属层布线不直接位于 金属垫。

公开(公告)号：US20150001675A1

公开(公告)日：2015-01-01

申请号：US14490690

申请日：2014-09-19

Applicant: MEDIATEK INC.

Inventor： Tien-Chang Chang ,  Ming-Tzong Yang ,  Tao Cheng ,  Cheng-Hsing Chien ,  Hsin-Hsin Hsiao

IPC: H01L49/02 ,  H01L27/06

CPC classification number: H01L28/40 ,  H01L27/0629 ,  H01L27/0811 ,  H01L29/94

Abstract: A semiconductor circuit comprises a first and a second logic circuit, a first and a second decoupling capacitor. The first decoupling capacitor is arranged in a first area around the first logic circuit and the second decoupling capacitor is arranged in a second area around the second logic circuit. Wherein, the first area is larger than the second area, a gate oxide thickness of the first decoupling capacitor is larger than a gate oxide thickness of the second decoupling capacitor, and a distance between the first area and the first logic circuit is shorter than a distance between the second area and the second logic circuit. Further, the first and second decoupling capacitors are designed without trench.

Abstract translation: 半导体电路包括第一和第二逻辑电路，第一和第二去耦电容器。 第一去耦电容器布置在第一逻辑电路周围的第一区域中，并且第二去耦电容器布置在第二逻辑电路周围的第二区域中。 其中，第一区域大于第二区域，第一去耦电容器的栅极氧化物厚度大于第二去耦电容器的栅极氧化物厚度，并且第一区域和第一逻辑电路之间的距离短于第 第二区域与第二逻辑电路之间的距离。 此外，第一和第二去耦电容器被设计成没有沟槽。