Video processing system with shared/configurable in-loop filter data buffer architecture and related video processing method thereof
    12.
    发明授权
    Video processing system with shared/configurable in-loop filter data buffer architecture and related video processing method thereof 有权
    具有共享/可配置的环路滤波器数据缓冲器架构的视频处理系统及其相关视频处理方法

    公开(公告)号:US09438911B2

    公开(公告)日:2016-09-06

    申请号:US13944893

    申请日:2013-07-18

    Applicant: MEDIATEK INC.

    CPC classification number: H04N19/80 H04N19/423

    Abstract: A video processing system includes a data buffer and a storage controller. The data buffer is shared between a plurality of in-loop filters, wherein not all of the in-loop filters comply with a same video standard. The storage controller controls data access of the data buffer, wherein for each in-loop filter granted to access the data buffer, the data buffer stores a partial data of a picture processed by the in-loop filter. Another video processing system includes a storage device and a storage controller. The storage controller adaptively determines a size of a storage space according to a tile partition setting of a picture to be processed by an in-loop filter, and controls the storage device to allocate the storage space to serve as a data buffer for storing data of the in-loop filter.

    Abstract translation: 视频处理系统包括数据缓冲器和存储控制器。 数据缓冲器在多个环路滤波器之间共享,其中并非所有的环路滤波器都符合相同的视频标准。 存储控制器控制数据缓冲器的数据访问,其中对于被授权访问数据缓冲器的每个环路滤波器,数据缓冲器存储由环路滤波器处理的图像的部分数据。 另一视频处理系统包括存储设备和存储控制器。 存储控制器根据由环路过滤器处理的图像的瓦片分区设置自适应地确定存储空间的大小,并且控制存储设备分配存储空间以用作用于存储数据的数据的数据缓冲器 内置滤波器。

    Method and apparatus for sample adaptive offset in a video decoder
    13.
    发明授权
    Method and apparatus for sample adaptive offset in a video decoder 有权
    视频解码器中样本自适应偏移的方法和装置

    公开(公告)号:US09344717B2

    公开(公告)日:2016-05-17

    申请号:US13887836

    申请日:2013-05-06

    Applicant: MEDIATEK INC.

    CPC classification number: H04N19/117 H04N19/423 H04N19/82 H04N19/86

    Abstract: A method and apparatus for SAO (sample adaptive offset) processing in a video decoder are disclosed. Embodiments according to the present invention reduce the required line buffer associated with the SAO processing. According to one embodiment, tri-level comparison results for one deblocked pixel row or column of the image unit are determined according to SAO type of the deblocked pixel row or column. The tri-level comparison results are stored in a buffer and the tri-level comparison results are read back from the buffer for SAO processing of the subsequent row or column from a subsequent image unit. The comparison results correspond to “larger”, “equal” and “smaller” states. The comparison results can be stored more efficiently.

    Abstract translation: 公开了一种用于视频解码器中的SAO(采样自适应偏移)处理的方法和装置。 根据本发明的实施例减少了与SAO处理相关联的所需线路缓冲器。 根据一个实施例,根据解锁像素行或列的SAO类型来确定图像单元的一个去块像素行或列的三电平比较结果。 三电平比较结果存储在缓冲器中,三级比较结果从缓冲器中读出,用于后续行或列从后续图像单元进行SAO处理。 比较结果对应于“较大”,“相等”和“较小”状态。 比较结果可以更有效地存储。

    VIDEO PROCESSING SYSTEM WITH SHARED/CONFIGURABLE IN-LOOP FILTER DATA BUFFER ARCHITECTURE AND RELATED VIDEO PROCESSING METHOD THEREOF
    14.
    发明申请
    VIDEO PROCESSING SYSTEM WITH SHARED/CONFIGURABLE IN-LOOP FILTER DATA BUFFER ARCHITECTURE AND RELATED VIDEO PROCESSING METHOD THEREOF 有权
    具有共享/可配置的内置滤波器数据缓冲器架构的视频处理系统及其相关视频处理方法

    公开(公告)号:US20140037017A1

    公开(公告)日:2014-02-06

    申请号:US13944893

    申请日:2013-07-18

    Applicant: MEDIATEK INC.

    CPC classification number: H04N19/80 H04N19/423

    Abstract: A video processing system includes a data buffer and a storage controller. The data buffer is shared between a plurality of in-loop filters, wherein not all of the in-loop filters comply with a same video standard. The storage controller controls data access of the data buffer, wherein for each in-loop filter granted to access the data buffer, the data buffer stores a partial data of a picture processed by the in-loop filter. Another video processing system includes a storage device and a storage controller. The storage controller adaptively determines a size of a storage space according to a tile partition setting of a picture to be processed by an in-loop filter, and controls the storage device to allocate the storage space to serve as a data buffer for storing data of the in-loop filter.

    Abstract translation: 视频处理系统包括数据缓冲器和存储控制器。 数据缓冲器在多个环路滤波器之间共享,其中并非所有的环路滤波器都符合相同的视频标准。 存储控制器控制数据缓冲器的数据访问,其中对于被授权访问数据缓冲器的每个环路滤波器,数据缓冲器存储由环路滤波器处理的图像的部分数据。 另一视频处理系统包括存储设备和存储控制器。 存储控制器根据由环路过滤器处理的图像的瓦片分区设置自适应地确定存储空间的大小,并且控制存储设备分配存储空间以用作用于存储数据的数据的数据缓冲器 内置滤波器。

    High efficiency adaptive loop filter processing for video coding

    公开(公告)号:US11051045B2

    公开(公告)日:2021-06-29

    申请号:US16815957

    申请日:2020-03-11

    Applicant: MEDIATEK INC.

    Abstract: A method and a circuit for adaptive loop filtering in a video coding system are described. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.

    High efficiency adaptive loop filter processing for video coding

    公开(公告)号:US10609417B2

    公开(公告)日:2020-03-31

    申请号:US15596752

    申请日:2017-05-16

    Applicant: MEDIATEK INC.

    Abstract: A method and a circuit for adaptive loop filtering in a video coding system are described. The method can include receiving a block of samples generated from a previous-stage filter circuit in a filter pipeline, the block of samples being one of multiple blocks included in a current picture, performing, in parallel, adaptive loop filter (ALF) processing for multiple target samples in the block of samples, while the previous-stage filter circuit is simultaneously processing another block in the current picture, storing, in a buffer, first samples each having a filter input area defined by a filter shape that includes at least one sample which has not been received, and storing, in the buffer, second samples included in the filter input areas of the first samples.

    Method and apparatus for arranging pixels of picture in storage units each having storage size not divisible by pixel size

    公开(公告)号:US10134107B2

    公开(公告)日:2018-11-20

    申请号:US14226840

    申请日:2014-03-27

    Applicant: MEDIATEK INC.

    Abstract: A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer.

    MIXED-LEVEL MULTI-CORE PARALLEL VIDEO DECODING SYSTEM
    18.
    发明申请
    MIXED-LEVEL MULTI-CORE PARALLEL VIDEO DECODING SYSTEM 审中-公开
    混合级多核并行视频解码系统

    公开(公告)号:US20160191922A1

    公开(公告)日:2016-06-30

    申请号:US14979546

    申请日:2015-12-28

    Applicant: MEDIATEK INC.

    Abstract: A method, apparatus and computer readable medium storing a corresponding computer program for decoding a video bitstream based on multiple decoder cores are disclosed. In one embodiment of the present invention, the method arranges multiple decoder cores to decode one or more frames from a video bitstream using mixed level parallel decoding. The multiple decoder cores are arranged into groups of multiple decoder cores for parallel decoding one or more frames by using one group of multiple decoder cores for said one or more frames, wherein each group of multiple decoder cores comprises one or more decoder cores. The number of frames to be decoded in the mixed level parallel decoding or which frames to be decoded in the mixed level parallel decoding is adaptively determined.

    Abstract translation: 公开了一种基于多个解码器核存储用于解码视频比特流的相应计算机程序的方法,装置和计算机可读介质。 在本发明的一个实施例中,该方法使用混合电平并行解码来设置多个解码器核来从视频比特流解码一个或多个帧。 多个解码器核被布置成多个解码器核心组,用于通过对于所述一个或多个帧使用一组多个解码器核来并行解码一个或多个帧,其中每组多个解码器核心包括一个或多个解码器核心。 在混合电平并行解码中要解码的帧的数量或在混合电平并行解码中要解码的帧被自适应地确定。

    METHOD AND APPARATUS FOR ARRANGING PIXELS OF PICTURE IN STORAGE UNITS EACH HAVING STORAGE SIZE NOT DIVISIBLE BY PIXEL SIZE
    19.
    发明申请
    METHOD AND APPARATUS FOR ARRANGING PIXELS OF PICTURE IN STORAGE UNITS EACH HAVING STORAGE SIZE NOT DIVISIBLE BY PIXEL SIZE 审中-公开
    用于安装存储单元中的图像像素的方法和装置,每个存储单元不能通过像素大小分辨

    公开(公告)号:US20140294090A1

    公开(公告)日:2014-10-02

    申请号:US14226840

    申请日:2014-03-27

    Applicant: MEDIATEK INC.

    Abstract: A data arrangement method includes following steps: obtaining pixel data of a plurality of first N-bit pixels of a picture; and storing the obtained pixel data of the first N-bit pixels in a plurality of M-bit storage units of a first buffer according to a block-based scan order of the picture. The picture includes a plurality of data blocks, and the block-based scan order includes a raster-scan order for the data blocks. At least one of the M-bit storage units is filled with part of the obtained pixel data of the first N-bit pixels, M and N are positive integers, M is not divisible by N, and the first N-bit pixels include at least one pixel divided into a first part stored in one of the M-bit storage units in the first buffer and a second part stored in another of the M-bit storage units in the first buffer.

    Abstract translation: 数据排列方法包括以下步骤:获得图像的多个第一N位像素的像素数据; 以及根据图像的基于块的扫描顺序将获得的第一N位像素的像素数据存储在第一缓冲器的多个M位存储单元中。 图像包括多个数据块,并且基于块的扫描顺序包括用于数据块的光栅扫描顺序。 M位存储单元中的至少一个被填充了所获得的第一N位像素的像素数据的一部分,M和N是正整数,M不能被N整除,并且第一N位像素包括在 至少一个像素被划分为存储在第一缓冲器中的M位存储单元之一中的第一部分和存储在第一缓冲器中的另一个M位存储单元中的第二部分。

    Method and Apparatus for Sample Adaptive Offset in a Video Decoder
    20.
    发明申请
    Method and Apparatus for Sample Adaptive Offset in a Video Decoder 有权
    视频解码器中采样自适应偏移的方法和装置

    公开(公告)号:US20140036991A1

    公开(公告)日:2014-02-06

    申请号:US13887836

    申请日:2013-05-06

    Applicant: MEDIATEK INC.

    CPC classification number: H04N19/117 H04N19/423 H04N19/82 H04N19/86

    Abstract: A method and apparatus for SAO (sample adaptive offset) processing in a video decoder are disclosed. Embodiments according to the present invention reduce the required line buffer associated with the SAO processing. According to one embodiment, tri-level comparison results for one deblocked pixel row or column of the image unit are determined according to SAO type of the deblocked pixel row or column. The tri-level comparison results are stored in a buffer and the tri-level comparison results are read back from the buffer for SAO processing of the subsequent row or column from a subsequent image unit. The comparison results correspond to “larger”, “equal” and “smaller” states. The comparison results can be stored more efficiently.

    Abstract translation: 公开了一种用于视频解码器中的SAO(采样自适应偏移)处理的方法和装置。 根据本发明的实施例减少了与SAO处理相关联的所需线路缓冲器。 根据一个实施例,根据解锁像素行或列的SAO类型来确定图像单元的一个去块像素行或列的三电平比较结果。 三电平比较结果存储在缓冲器中,三级比较结果从缓冲器中读出,用于后续行或列从后续图像单元进行SAO处理。 比较结果对应于“较大”,“相等”和“较小”状态。 比较结果可以更有效地存储。

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