公开(公告)号：US10979030B2

公开(公告)日：2021-04-13

申请号：US16044731

申请日：2018-07-25

Applicant: MEDIATEK Inc.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03H17/00 ,  H03H17/04 ,  H03H17/02 ,  H03M7/36 ,  H03M3/00 ,  H04B14/06 ,  H03M7/32

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

公开(公告)号：US20160056783A1

公开(公告)日：2016-02-25

申请号：US14467066

申请日：2014-08-25

Applicant: MEDIATEK INC.

Inventor： Chi-Yun Wang ,  Chih-Hong Lou ,  Yen-Chuan Huang ,  Li-Han Hung

IPC: H03G3/30 ,  H03F3/45 ,  H03F1/56

CPC classification number: H03G3/30 ,  H03B5/24 ,  H03F1/56 ,  H03F3/45475 ,  H03F2203/45116 ,  H03F2203/45118 ,  H03F2203/45526

Abstract: A resonating device includes: an amplifying circuit having a first input terminal, and an output terminal for outputting an output signal; a first feedback circuit coupled between the first input terminal and the output terminal of the amplifying circuit; a second feedback circuit, coupled between the first input terminal and the output terminal of the amplifying circuit; and a gain adjusting circuit, having an input terminal for receiving an input signal, and a first output terminal coupled to the first input terminal of the amplifying circuit; wherein a first equivalent impedance on a first intermediate terminal in the first feedback circuit substantially equals a second equivalent impedance on a second intermediate terminal in the second feedback circuit, and the gain adjusting circuit is arranged to tune a transfer function from the input signal to the output signal.

Abstract translation: 谐振装置包括：具有第一输入端的放大电路和用于输出输出信号的输出端; 耦合在放大电路的第一输入端和输出端之间的第一反馈电路; 耦合在放大电路的第一输入端和输出端之间的第二反馈电路; 以及增益调整电路，具有用于接收输入信号的输入端子和耦合到放大电路的第一输入端子的第一输出端子; 其中所述第一反馈电路中的第一中间端子上的第一等效阻抗基本上等于所述第二反馈电路中的第二中间端子上的第二等效阻抗，并且所述增益调整电路被布置成将传递函数从所述输入信号调谐到 输出信号。

公开(公告)号：US10579084B2

公开(公告)日：2020-03-03

申请号：US16181350

申请日：2018-11-06

Applicant: MEDIATEK INC.

Inventor： Kuan-Chun Chen ,  Chih-Hong Lou

IPC: G05F1/61 ,  G05F1/614 ,  G05F1/575 ,  G05F1/618 ,  G05F1/563 ,  G05F1/46

Abstract: A voltage regulator apparatus includes operational amplifier, first resistor, second resistor, driving transistor, amplifier circuit, and output circuit. The operational amplifier has first input terminal coupled to reference voltage, second input terminal, and output terminal. The first resistor has first terminal coupled to second input terminal. The second resistor is coupled between first resistor and ground level. The driving transistor has control terminal coupled to output terminal of operational amplifier and first terminal coupled to second terminal of first resistor. The amplifier circuit is coupled to output terminal of operational amplifier and configured to sense output voltage of voltage regulator apparatus to amplify the sensed voltage with specific gain to regulate a transistor of output circuit. The transistor has control terminal controlled by amplifier circuit. The output voltage is generated at first terminal of the transistor.

公开(公告)号：US20190235543A1

公开(公告)日：2019-08-01

申请号：US16181350

申请日：2018-11-06

Applicant: MEDIATEK INC.

Inventor： Kuan-Chun Chen ,  Chih-Hong Lou

IPC: G05F1/56 ,  H03F3/45

Abstract: A voltage regulator apparatus includes operational amplifier, first resistor, second resistor, driving transistor, amplifier circuit, and output circuit. The operational amplifier has first input terminal coupled to reference voltage, second input terminal, and output terminal. The first resistor has first terminal coupled to second input terminal. The second resistor is coupled between first resistor and ground level. The driving transistor has control terminal coupled to output terminal of operational amplifier and first terminal coupled to second terminal of first resistor. The amplifier circuit is coupled to output terminal of operational amplifier and configured to sense output voltage of voltage regulator apparatus to amplify the sensed voltage with specific gain to regulate a transistor of output circuit. The transistor has control terminal controlled by amplifier circuit. The output voltage is generated at first terminal of the transistor.

公开(公告)号：US20160056835A1

公开(公告)日：2016-02-25

申请号：US14600017

申请日：2015-01-20

Applicant: MEDIATEK INC.

Inventor： Li-Han Hung ,  Yen-Chuan Huang ,  Chi-Yun Wang ,  Chih-Hong Lou

IPC: H03M3/00

CPC classification number: H03M3/354 ,  H03H11/1252 ,  H03M3/404 ,  H03M3/438

Abstract: A signal modulating device includes: an integrating circuit arranged to generate an integrated signal according to a scaled analog signal and a first feedback signal; a resonating circuit arranged to generate a resonating signal according to the integrated signal; a first signal converting circuit arranged to convert the resonating signal into a digital output signal; a second signal converting circuit arranged to convert the digital output signal into the first feedback signal; and a first impedance circuit having a first terminal receiving an analog signal and a second terminal coupled to the resonating circuit for altering the location of zeros in the forward-path transfer function and consequently shaping the signal transfer function (STF) of the signal modulating device; and a second impedance circuit having a first terminal receiving the analog signal and a second terminal coupled to the integrating circuit for generating the scaled analog signal.

Abstract translation: 信号调制装置包括：积分电路，被配置为根据缩放的模拟信号和第一反馈信号产生积分信号; 谐振电路，被布置成根据积分信号产生谐振信号; 布置成将所述谐振信号转换为数字输出信号的第一信号转换电路; 布置成将数字输出信号转换成第一反馈信号的第二信号转换电路; 以及第一阻抗电路，其具有接收模拟信号的第一端子和耦合到所述谐振电路的第二端子，用于改变所述前向路径传递函数中的零点的位置，并因此整形所述信号调制装置的信号传递函数（STF） ; 以及第二阻抗电路，其具有接收模拟信号的第一端子和耦合到积分电路的第二端子，用于产生经缩放的模拟信号。

公开(公告)号：US09263995B2

公开(公告)日：2016-02-16

申请号：US14073148

申请日：2013-11-06

Applicant: MediaTek Inc.

Inventor： Chi Yun Wang ,  Chih-Hong Lou

IPC: H03F1/14 ,  H03F1/34 ,  H03F1/48 ,  H03F3/45

CPC classification number: H03F1/34 ,  H03F1/14 ,  H03F1/486 ,  H03F3/45475 ,  H03F3/45941 ,  H03F3/45946 ,  H03F2203/45138 ,  H03F2203/45512 ,  H03F2203/45514 ,  H03F2203/45576 ,  H03F2203/45644

Abstract: A multi-mode OPAMP-based circuit is provided. An input amplifying stage amplifies a pair of input differential signals to provide a pair of intermediate differential signals. An output amplifying stage amplifies the pair of intermediate differential signals to provide a pair of output differential signals. A first capacitor is disposed in a first negative feedback loop of the output amplifying stage. A second capacitor is disposed in a second negative feedback loop of the output amplifying stage. A third capacitor is selectively disposed in a first positive feedback loop of the output amplifying stage or coupled to the first capacitor in parallel according to a control signal. A fourth capacitor is selectively disposed in a second positive feedback loop of the output amplifying stage or coupled to the second capacitor in parallel according to the control signal.

Abstract translation: 提供了基于多模式OPAMP的电路。 输入放大级放大一对输入差分信号以提供一对中间差分信号。 输出放大级放大一对中间差分信号以提供一对输出差分信号。 第一电容器设置在输出放大级的第一负反馈回路中。 第二电容器设置在输出放大级的第二负反馈回路中。 第三电容器选择性地设置在输出放大级的第一正反馈环路中，或者根据控制信号并联耦合到第一电容器。 第四电容器选择性地设置在输出放大级的第二正反馈环路中，或者根据控制信号并联耦合到第二电容器。

公开(公告)号：US20150303880A1

公开(公告)日：2015-10-22

申请号：US14259120

申请日：2014-04-22

Applicant: MEDIATEK INC.

Inventor： Tzu-Hsuin Peng ,  Chih-Hong Lou ,  Chao-Hsin Lu ,  Chi-Yun Wang ,  Chih-Jung Chen

IPC: H03F1/26 ,  H03H11/04 ,  H03H11/12 ,  H03F3/45

CPC classification number: H03F1/26 ,  H03F3/45475 ,  H03F3/45479 ,  H03F3/45932 ,  H03F2200/129 ,  H03F2200/267 ,  H03F2203/45061 ,  H03F2203/45116 ,  H03F2203/45138 ,  H03F2203/45526 ,  H03H11/0405 ,  H03H11/1217 ,  H03H11/1234

Abstract: A low pass filter includes a first amplifier stage and a second amplifier stage. The first amplifier stage includes a differential operational amplifier, wherein the first amplifier stage is arranged to process a differential input signal to generate a differential intermediate signal, the differential input signal having a first input signal and a second input signal, and the differential intermediate signal having a first intermediate signal and a second intermediate signal. The second amplifier stage has no common-mode feedback and is arranged to process the differential intermediate signal to generate a differential output signal, wherein the differential output signal has a first output signal corresponding to the first input signal and a second output signal corresponding to the second input signal. Since the noisy common-mode feedback is removed from the second amplifier stage, the overall common-mode noise of the low pass filter can be decreased.

Abstract translation: 低通滤波器包括第一放大级和第二放大级。 第一放大器级包括差分运算放大器，其中第一放大器级被布置成处理差分输入信号以产生差分中间信号，差分输入信号具有第一输入信号和第二输入信号，以及差分中间信号 具有第一中间信号和第二中间信号。 第二放大器级没有共模反馈，并且被布置成处理差分中间信号以产生差分输出信号，其中差分输出信号具有对应于第一输入信号的第一输出信号和对应于第一输入信号的第二输出信号 第二输入信号。 由于从第二放大器级除去噪声共模反馈，所以可以降低低通滤波器的总体共模噪声。

公开(公告)号：US20210265982A1

公开(公告)日：2021-08-26

申请号：US17196946

申请日：2021-03-09

Applicant: MediaTek Inc.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03H17/02 ,  H03M7/36 ,  H03H17/04 ,  H03H17/00 ,  H03M3/00 ,  H04B14/06 ,  H03M7/32

Abstract: The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

公开(公告)号：US20210216092A1

公开(公告)日：2021-07-15

申请号：US17065445

申请日：2020-10-07

Applicant: MediaTek Inc.

Inventor： Po-Jung Chang ,  Yan-Jiun Chen ,  Chih-Hong Lou

IPC: G05F1/575

Abstract: A low-dropout regulator (LDO) capable of providing high power-supply rejection ratio (PSRR) and good reverse isolation. The LDO may include a core circuitry and a reverse isolation circuitry. The core circuitry may include a PSRR circuitry coupled to an output node and configured to provide high PSRR at the output node. The reverse isolation circuitry may be configured to provide good reverse isolation at the output node by, for example, providing current in response to ripples at the output node. The reverse isolation circuitry may be configured with bandwidth higher than that of the core circuitry such that it can provide fast transient response. The reverse isolation circuitry may be configurable and/or reconfigurable for a desirable reverse isolation performance. The reverse isolation circuitry may be configurable and/or reconfigurable to trade off between power consumed by the reverse isolation circuitry and a leakage current flowing through the core circuitry.

公开(公告)号：US09871534B2

公开(公告)日：2018-01-16

申请号：US15499872

申请日：2017-04-27

Applicant: MEDIATEK INC.

Inventor： Jen-Huan Tsai ,  Chih-Hong Lou

IPC: H03M3/00 ,  H03M1/12 ,  H03M1/46

CPC classification number: H03M3/426 ,  H03M1/1245 ,  H03M1/466 ,  H03M3/338 ,  H03M3/37 ,  H03M3/412 ,  H03M3/424 ,  H03M3/458

Abstract: An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.