公开(公告)号：US20060087570A1

公开(公告)日：2006-04-27

申请号：US10905969

申请日：2005-01-28

Applicant: Kuo-Yu Chou ,  Chih-Hua Tsai

Inventor： Kuo-Yu Chou ,  Chih-Hua Tsai

IPC: H04N9/64

CPC classification number: H04N5/367 ,  H04N1/401

Abstract: An image sensing device includes a pixel sensing data processing unit, for receiving a pixel line sensing data to output first and second outputs. A controller receives the first output from the pixel sensing data processing unit, checks whether the pixel line sensing data include at least one defective pixel. If it has defective pixel, a correction rule is applied to compare the status data with a previously defective pixel. The correction rule includes comparing a state data of the previous defect pixels. If the defective pixel belongs to a regular pattern, the defective pixel is not corrected. A correction unit receives the second output and receives the correction status from the controller, and to correct the pixel and exports a display data. A recording unit records the status data of the defective pixel detected by the controller for comparing the status data of the next pixel line sensing data.

Abstract translation: 图像感测装置包括像素感测数据处理单元，用于接收像素线感测数据以输出第一和第二输出。 控制器从像素感测数据处理单元接收第一输出，检查像素线感测数据是否包括至少一个缺陷像素。 如果它具有缺陷像素，则应用校正规则来将状态数据与先前缺陷的像素进行比较。 校正规则包括比较先前缺陷像素的状态数据。 如果缺陷像素属于规则图案，则不校正缺陷像素。 校正单元接收第二输出并从控制器接收校正状态，并校正像素并输出显示数据。 记录单元记录用于比较下一个像素行感测数据的状态数据的控制器检测到的缺陷像素的状态数据。

公开(公告)号：US20090244335A1

公开(公告)日：2009-10-01

申请号：US12125914

申请日：2008-05-23

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H04N3/14

CPC classification number: H04N5/2173 ,  H04N5/3575 ,  H04N5/363 ,  H04N5/374 ,  H04N5/378

Abstract: Embodiments of the present invention provide a correlated double sampling (CDS) circuit and a CMOS image sensor unit using the CDS circuit. The CDS circuit shifts levels of sampled sensing signal and reset signal with equal amounts. Thus a voltage difference of the sampled sensing signal and the reset signal remains unchanged, and their levels may fall within a linear input range by adjusting their levels. Compared to a conventional CDS circuit, a gain of the CDS circuit provided by the embodiment of the present invention is not reduced, and thus a design complexity of a rear circuit thereof is lower, and an induced noise is relatively low. Furthermore, the CMOS image sensor unit using the CDS circuit provided by the embodiment also has these advantages.

Abstract translation: 本发明的实施例提供了一种使用CDS电路的相关双采样（CDS）电路和CMOS图像传感器单元。 CDS电路使采样的感测信号和复位信号的电平相等。 因此，采样的感测信号和复位信号的电压差保持不变，并且它们的电平可以通过调整它们的电平而落在线性输入范围内。 与传统的CDS电路相比，本发明实施例提供的CDS电路的增益不会降低，因此其后部电路的设计复杂度较低，并且感应噪声相对较低。 此外，使用本实施例提供的CDS电路的CMOS图像传感器单元也具有这些优点。

公开(公告)号：US20080079832A1

公开(公告)日：2008-04-03

申请号：US11682280

申请日：2007-03-05

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L27/00 ,  H04N5/335 ,  H04N3/14

CPC classification number: H04N9/045 ,  H04N5/3742 ,  H04N5/378

Abstract: A CMOS image sensor having two ASPs can reduce increasing design difficulty as arising from a pixel array becoming larger and larger. The image sensor includes a selection circuit for transmitting outputs of CDS circuits through four divided buses to reduce parasitic loading and achieve high-speed operation. Then, the selecting circuit transmits red and blue pixels to a first ASP, and transmits green pixels to a second ASP, so as to relax the specification requirements of the ASP.

Abstract translation: 具有两个ASP的CMOS图像传感器可以减少由于像素阵列变得越来越大而引起的增加的设计难度。 图像传感器包括用于通过四个分开的总线传输CDS电路的输出以减少寄生负载并实现高速操作的选择电路。 然后，选择电路将红色和蓝色像素传输到第一ASP，并将绿色像素发送到第二ASP，以便放宽ASP的规范要求。

公开(公告)号：US20070257999A1

公开(公告)日：2007-11-08

申请号：US11428573

申请日：2006-07-05

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H04N5/335

CPC classification number: H04N5/335 ,  H03F1/0277 ,  H03F3/72 ,  H03F2200/552 ,  H03F2203/7231 ,  H03F2203/7236 ,  H03F2203/7239 ,  H03G1/0088 ,  H04N5/243 ,  H04N5/378

Abstract: A variable-gain amplifier circuit and a method of changing gain amplifier paths are provided for receiving and amplifying an image sensing signal. The variable-gain amplifier circuit includes variable path and gain amplifier circuits. According to the amplification factor for the image sensing signal, the gain amplifier paths in the variable path and gain amplifier circuits are changed based on a control signal, so as to achieve the appropriate construction of the variable-gain amplifier circuit. The image sensing signal generates the required image result through appropriate numbers of variable gain amplifiers, thereby decreasing the power consumption of the circuit and reducing the design requirement of the circuit.

Abstract translation: 提供可变增益放大器电路和改变增益放大器路径的方法，用于接收和放大图像感测信号。 可变增益放大器电路包括可变路径和增益放大器电路。 根据图像感测信号的放大系数，可变路径和增益放大器电路中的增益放大器路径基于控制信号而改变，以便实现可变增益放大器电路的适当构造。 图像感测信号通过适当数量的可变增益放大器产生所需的图像结果，从而降低电路的功耗并降低电路的设计要求。

公开(公告)号：US06710727B1

公开(公告)日：2004-03-23

申请号：US10369643

申请日：2003-02-21

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H03M110

CPC classification number: H03M1/0697 ,  H03M1/462

Abstract: The present invention provides a correction system and method for a Successive Approximation A/D Converter (SA-ADC) of the prior art. The operation method of the correction system is described in the following: (1) Using the SA-ADC of the prior art to convert an analog signal to a digital data. The digital data is a series of logic numbers. (2) Detecting the last number of the digital data is logic number [0] or logic number [1]. (3-1) When the last number is logic number [1], proceeding the digital data and logic number [1] with an addition operation to generate a first detection digital data. Converting the first detection digital data to a first detection signal for comparing with the analog signal. If the analog signal is higher than the first detection signal, then replacing the digital data by the first detection digital data. If the analog signal is lower than the first detection signal, then outputting the digital data without correcting. (3-2) When the last number is logic number [0], using the digital data to detect directly. Converting the digital data to a second detection signal for comparing with the analog signal. If the analog signal is higher than the second detection signal, then outputting the digital data without correcting. If the analog signal is lower than the first detection signal, then proceeding the digital data and logic number [1] with a subtraction operation to generate a second detection digital data to replace the digital data.

Abstract translation: 本发明提供了现有技术的连续近似A / D转换器（SA-ADC）的校正系统和方法。 以下描述校正系统的操作方法：（1）使用现有技术的SA-ADC将模拟信号转换为数字数据。 数字数据是一系列逻辑数字。 （2）检测数字数据的最后一个数字是逻辑号[0]或逻辑号[1]。 （3-1）当最后一个数字为逻辑编号[1]时，用加法运算进行数字数据和逻辑编号[1]，生成第一个检测数字数据。 将第一检测数字数据转换为与模拟信号进行比较的第一检测信号。 如果模拟信号高于第一检测信号，则用第一检测数字数据替换数字数据。 如果模拟信号低于第一检测信号，则输出数字数据而不进行校正。 （3-2）当最后一个数字为逻辑号[0]时，使用数字数据直接检测。 将数字数据转换为与模拟信号进行比较的第二检测信号。 如果模拟信号高于第二检测信号，则输出数字数据而不进行校正。 如果模拟信号低于第一检测信号，则通过减法运算进行数字数据和逻辑编号[1]，生成第二检测数字数据，以代替数字数据。

公开(公告)号：US06424574B1

公开(公告)日：2002-07-23

申请号：US09865565

申请日：2001-05-29

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: G11C1600

CPC classification number: G11C16/3445 ,  G11C16/16 ,  G11C16/344

Abstract: The present invention provides a method of erasing data in a flash memory. The flash memory has a number of memory units for storing data. The method has involves repeatedly performing an erasing process along a first erasing route to erase data stored in each memory unit, and if after a predetermined number of erasing times, data in each memory unit is not completely erased, a second erasing route to perform the erasing process is utilized.

Abstract translation: 本发明提供一种擦除闪速存储器中的数据的方法。 闪存具有用于存储数据的多个存储单元。 该方法包括重复执行沿着第一擦除路线的擦除处理以擦除存储在每个存储单元中的数据，并且如果在预定数量的擦除时间之后，每个存储器单元中的数据未被完全擦除，则执行第二擦除路线 使用擦除过程。

公开(公告)号：US06407948B1

公开(公告)日：2002-06-18

申请号：US09683079

申请日：2001-11-15

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: G11C1634

CPC classification number: G11C16/3409 ,  G11C16/3404

Abstract: A flash memory circuit has a flash memory array and a processor. The flash memory array has a plurality of erasable flash memory cells. Each of the flash memory cells is electrically connected to a corresponding bitline. If any over-erased flash memory cell exists in the flash memory array, a processor controls the flash memory circuit to apply a correction voltage to the bitline connected to the over-erased flash memory cell so as to correct the over-erased flash memory cell. The correction voltage is continuously applied until a current along the corresponding bitline drops below a predetermined value.

Abstract translation: 闪存电路具有闪存阵列和处理器。 闪存阵列具有多个可擦除闪存单元。 每个闪存单元电连接到相应的位线。 如果闪速存储器阵列中存在任何过擦除的闪速存储器单元，则处理器控制闪速存储器电路将校正电压施加到连接到过擦除闪存单元的位线，以便校正过擦除的闪存单元 。 连续施加校正电压，直到沿着相应位线的电流下降到预定值以下。

公开(公告)号：US06236297B1

公开(公告)日：2001-05-22

申请号：US09136505

申请日：1998-08-19

Applicant: Kuo-Yu Chou ,  Shyang Su ,  Jen-Tsai Kuo

Inventor： Kuo-Yu Chou ,  Shyang Su ,  Jen-Tsai Kuo

IPC: H01F2728

CPC classification number: H01F17/0006 ,  H01L23/5227 ,  H01L23/645 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A combinational inductor, which can be constructed on a surface of a semiconductor substrate or an isolator, is provided. The combinational inductor includes several spiral inductors which are connected together in series. The spiral inductors can be constructed on the same layer to produce a combinational inductor structure, because of the same metalization process used. In another aspect, connecting methods between neighboring spiral conductors include forward cascade and reverse cascade. A spiral conductor has at least one neighboring spiral conductor which is connected with it in reverse cascade. The inductance per unit square measurement of the inductor in series can be significantly increased through the connections between neighboring spiral conductors either in forward cascade or reverse cascade.

Abstract translation: 提供了可以构造在半导体衬底或隔离器的表面上的组合电感器。 组合电感器包括串联连接在一起的多个螺旋电感器。 由于使用相同的金属化工艺，螺旋电感器可以构造在同一层上以产生组合电感器结构。 另一方面，相邻螺旋导体之间的连接方法包括向前级联和反向级联。 螺旋导体具有至少一个相邻的螺旋导体，其以反向级联连接。 串联的电感器每单位平方测量的电感可以通过前级联或反向级联的相邻螺旋导体之间的连接显着增加。

公开(公告)号：US5998285A

公开(公告)日：1999-12-07

申请号：US126199

申请日：1998-07-30

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423

CPC classification number: H01L29/6659 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/66545 ,  H01L21/2255

Abstract: A process is disclosed for the fabrication of a MOS device with a T-shaped gate electrode, in which a selective CVD technique has been utilized to simplify the T-shaped gate process. After the formation of the gate oxide layer, no reactive ion etching step is applied, and that avoids the plasma charging damage to the gate oxide. The lightly-doped-drain structure and heavily-doped drain and source areas are formed in a self-aligned manner during the T-shaped gate process. The present invention provides a high yield rate and cost-saving in the T-shaped gate process for MOS devices.

Abstract translation: 公开了一种用于制造具有T形栅电极的MOS器件的工艺，其中已经利用选择性CVD技术来简化T形栅极工艺。 形成栅氧化层之后，不施加反应离子蚀刻步骤，避免了对栅极氧化物的等离子体充电损伤。 在T形栅极工艺期间，轻掺杂漏极结构和重掺杂漏极和源极区域以自对准的方式形成。 本发明在MOS器件的T形栅极工艺中提供了高产率和低成本。

公开(公告)号：US07777559B2

公开(公告)日：2010-08-17

申请号：US11855142

申请日：2007-09-13

Applicant: Kuo-Yu Chou

Inventor： Kuo-Yu Chou

IPC: G05F1/10

CPC classification number: G05F3/24

Abstract: To mitigate kickback noise effect, the present invention provides a reference voltage generator for an analog-to-digital converter circuit. The reference voltage generator includes a bias generator, a bias converter and an output unit. The bias generator is used for generating a first bias voltage in accordance with a reference voltage. The bias converter is coupled to the bias generator and is used for converting the first bias voltage to a second bias voltage. The output unit is coupled to the bias converter and used for generating a first voltage to a load circuit in accordance with the second bias voltage.

Abstract translation: 为了减轻反冲噪声效应，本发明提供了一种用于模数转换器电路的参考电压发生器。 参考电压发生器包括偏置发生器，偏置转换器和输出单元。 偏置发生器用于根据参考电压产生第一偏置电压。 偏置转换器耦合到偏置发生器，并用于将第一偏置电压转换为第二偏置电压。 输出单元耦合到偏置转换器，用于根据第二偏置电压向负载电路产生第一电压。