公开(公告)号：US07356793B2

公开(公告)日：2008-04-08

申请号：US11129784

申请日：2005-05-16

申请人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. McIlvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

发明人： James J. Curtin ,  Michael J. Cadigan, Jr. ,  Edward J. Hughes ,  Kevin M. McIlvain ,  Jose L. Neves ,  Ray Raphy ,  Douglas S. Search

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US07519927B1

公开(公告)日：2009-04-14

申请号：US12166561

申请日：2008-07-02

申请人： John N. Hryckowian ,  Heidi L. Lagares-Vazquez ,  Ray Raphy ,  Alan Daniel Stigliani ,  Charles Vakirtzis

发明人： John N. Hryckowian ,  Heidi L. Lagares-Vazquez ,  Ray Raphy ,  Alan Daniel Stigliani ,  Charles Vakirtzis

IPC分类号： G06F17/50

CPC分类号： G06F17/5077 ,  G06F2217/62

摘要： Wiring structures and methods for integrated circuit designs which are adapted to reduce metal variation effects on launch-capture clock pairs in order to minimize cycle time overlap violations in launch/capture clocking systems are provided, whereby the A/B/C (test/launch/capture) clock wire nets are designed using a five parallel track wire segment, in which the B clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, the C clock wire is represented as a double track with one metal track and one adjacent isolation/shielding track, and where the A test clock wire is represented as a single track comprising test signal wire disposed between the B and C signal wires.

摘要翻译： 提供了用于集成电路设计的接线结构和方法，其适于减少对发射捕获时钟对的金属变化影响，以便最小化发射/捕获时钟系统中的周期时间重叠违例，由此A / B / C（测试/发射 /捕获）时钟线网使用五个平行轨道线段设计，其中B时钟线表示为具有一个金属轨道和一个相邻隔离/屏蔽轨道的双轨道，C时钟线表示为双轨道 具有一个金属轨道和一个相邻的隔离/屏蔽轨道，并且其中A测试时钟线被表示为包括设置在B和C信号线之间的测试信号线的单个轨道。

公开(公告)号：US20060010410A1

公开(公告)日：2006-01-12

申请号：US11129784

申请日：2005-05-16

申请人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

发明人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： Genie is a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US20080066036A1

公开(公告)日：2008-03-13

申请号：US11934995

申请日：2007-11-05

申请人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

发明人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin McIlvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： An integrated Circlet chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： 使用Genie制作的集成Circlet芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。

公开(公告)号：US20080052655A1

公开(公告)日：2008-02-28

申请号：US11876400

申请日：2007-10-22

申请人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin Mcllvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

发明人： James Curtin ,  Michael Cadigan ,  Edward Hughes ,  Kevin Mcllvain ,  Jose Neves ,  Ray Raphy ,  Douglas Search

IPC分类号： G06F17/50

CPC分类号： B62K25/286 ,  B62K3/02 ,  G06F17/5031

摘要： An integrated circuit chip is made using Genie, a described computer chip design tool which can analyze the data contained within an entire endpoint report, compute relationships between paths based on shared segments, and display this information graphically to the designer. Specifically, Genie groups failing paths into Timing Islands. A timing island is a group of paths which contain at least one shared segment. The most frequently shared segment is sifted to the top of the priority list for each island, and is labeled as the Hub. Thinking of timing islands as a tree, the hub of the island would be the trunk. If you chop the tree down by the trunk, all of the branches, limbs and twigs will fall down too. This is analogous to fixing the timing failures in the hub, and the fix trickling out to each of the segments that dangle off the hub.

摘要翻译： 使用Genie制造的集成电路芯片，Genie是一种描述的计算机芯片设计工具，可以分析整个端点报告中包含的数据，计算基于共享段的路径之间的关系，并将图形显示给设计者。 具体来说，Genie团体失败了进入时代岛的路径。 定时岛是包含至少一个共享段的一组路径。 最常见的共享段被筛选到每个岛的优先级列表的顶部，并被标记为Hub。 将定时岛作为一棵树，岛上的中心将是树干。 如果树干被树干砍下来，所有的树枝，四肢和树枝也会掉下来。 这类似于在集线器中修复定时故障，并且修复程序会逐渐转移到每个从集线器上散落的段。