公开(公告)号：US10423411B2

公开(公告)日：2019-09-24

申请号：US14866921

申请日：2015-09-26

Applicant: Intel Corporation

Inventor： Asit K. Mishra ,  Edward T. Grochowski ,  Jonathan D. Pearce ,  Deborah T. Marr ,  Ehud Cohen ,  Elmoustapha Ould-Ahmed-Vall ,  Jesus Corbal San Adrian ,  Robert Valentine ,  Mark J. Charney ,  Christopher J. Hughes ,  Milind B. Girkar

IPC: G06F9/30

Abstract: A processor includes a decode unit to decode an instruction that is to indicate a first source packed data operand that is to include at least four data elements, to indicate a second source packed data operand that is to include at least four data elements, and to indicate one or more destination storage locations. The execution unit, in response to the instruction, is to store at least one result mask operand in the destination storage location(s). The at least one result mask operand is to include a different mask element for each corresponding data element in one of the first and second source packed data operands in a same relative position. Each mask element is to indicate whether the corresponding data element in said one of the source packed data operands equals any of the data elements in the other of the source packed data operands.

公开(公告)号：US11693691B2

公开(公告)日：2023-07-04

申请号：US17381521

申请日：2021-07-21

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/48 ,  G06F9/3001 ,  G06F9/3004 ,  G06F9/30036 ,  G06F9/383

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US11294670B2

公开(公告)日：2022-04-05

申请号：US16366155

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Christopher J. Hughes ,  Jonathan D. Pearce ,  Guei-Yuan Lueh ,  ElMoustapha Ould-Ahmed-Vall ,  Jorge E. Parra ,  Prasoonkumar Surti ,  Krishna N. Vinod ,  Ronen Zohar

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.

公开(公告)号：US11093277B2

公开(公告)日：2021-08-17

申请号：US16913265

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Rajesh M. Sankaran ,  Gilbert Neiger ,  Narayan Ranganathan ,  Stephen R. Van Doren ,  Joseph Nuzman ,  Niall D. McDonnell ,  Michael A. O'Hanlon ,  Lokpraveen B. Mosur ,  Tracy Garrett Drysdale ,  Eriko Nurvitadhi ,  Asit K. Mishra ,  Ganesh Venkatesh ,  Deborah T. Marr ,  Nicholas P. Carter ,  Jonathan D. Pearce ,  Edward T. Grochowski ,  Richard J. Greco ,  Robert Valentine ,  Jesus Corbal ,  Thomas D. Fletcher ,  Dennis R. Bradford ,  Dwight P. Manley ,  Mark J. Charney ,  Jeffrey J. Cook ,  Paul Caprioli ,  Koichi Yamada ,  Kent D. Glossop ,  David B. Sheffield

IPC: G06F9/48 ,  G06F9/30 ,  G06F9/38

Abstract: Embodiments of systems, methods, and apparatuses for heterogeneous computing are described. In some embodiments, a hardware heterogeneous scheduler dispatches instructions for execution on one or more plurality of heterogeneous processing elements, the instructions corresponding to a code fragment to be processed by the one or more of the plurality of heterogeneous processing elements, wherein the instructions are native instructions to at least one of the one or more of the plurality of heterogeneous processing elements.

公开(公告)号：US10896141B2

公开(公告)日：2021-01-19

申请号：US16364725

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Jeffrey J. Cook ,  Jonathan D. Pearce ,  Srikanth T. Srinivasan ,  Rishiraj A. Bheda ,  David B. Sheffield ,  Abhijit Davare ,  Anton Alexandrovich Sorokin

IPC: G06F13/16 ,  G06F9/38 ,  H04L9/06 ,  G06F12/0815

Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.

公开(公告)号：US20200310992A1

公开(公告)日：2020-10-01

申请号：US16364725

申请日：2019-03-26

Applicant: Intel Corporation

Inventor： Jeffrey J. Cook ,  Jonathan D. Pearce ,  Srikanth T. Srinivasan ,  Rishiraj A. Bheda ,  David B. Sheffield ,  Abhijit Davare ,  Anton Alexandrovich Sorokin

IPC: G06F13/16 ,  G06F9/38 ,  G06F12/0815 ,  H04L9/06

Abstract: In one embodiment, a cache memory includes: a plurality of data banks, each of the plurality of data banks having a plurality of entries each to store a portion of a cache line distributed across the plurality of data banks; and a plurality of tag banks decoupled from the plurality of data banks, wherein a tag for a cache line is to be assigned to one of the plurality of tag banks. Other embodiments are described and claimed.