公开(公告)号：US20160246609A1

公开(公告)日：2016-08-25

申请号：US15024143

申请日：2013-11-15

Applicant: Intel Corporation

Inventor： Yihua Jin ,  Jianhui Li ,  Tingtao Li ,  Xiaodong Lin

IPC: G06F9/445 ,  G06F9/44 ,  G06F3/0488

CPC classification number: G06F9/445 ,  G06F3/04883 ,  G06F9/451 ,  G06F9/45545

Abstract: Methods and apparatus relating to seamless host system gesture experience for guest applications on touch based devices are described. In an embodiment, Host Gesture Capture (HGC) logic detects a gesture in response to a touch event. The HGC logic forwards the gesture to Host Gesture Emulator (HGE) logic in response to a determination that the gesture is unrelated to an operation of a host system. The HGE logic operates in accordance with a guest operating system of the host system. Other embodiments are also claimed and described.

Abstract translation: 描述与基于触摸的设备上的访客应用的无缝主机系统手势体验相关的方法和装置。 在一个实施例中，主机手势捕获（HGC）逻辑检测响应于触摸事件的手势。 响应于确定手势与主机系统的操作无关，HGC逻辑将手势转发到主机手势仿真器（HGE）。 HGE逻辑根据主机系统的客户操作系统进行操作。 还要求保护和描述其它实施例。

公开(公告)号：US12079138B2

公开(公告)日：2024-09-03

申请号：US17892879

申请日：2022-08-22

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/30 ,  G06F9/355 ,  G06F9/455

CPC classification number: G06F12/10 ,  G06F9/30174 ,  G06F9/355 ,  G06F9/45554 ,  G06F9/45558 ,  G06F2009/45583

Abstract: An example system includes: interface circuitry; programmable circuitry; and instructions to cause the programmable circuitry to: reserve first memory addresses of a host system, the first memory addresses reserved for emulation of a guest system, the guest system based on a first instruction set architecture that is different from a second instruction set architecture of the host system; reserve second memory addresses of the host system that are contiguous with the first memory addresses, the second memory addresses reserved for a first emulated memory access instruction associated with an overflow in the guest system; reserve third memory addresses of the host system for a second emulated memory access instruction associated with an underflow in the guest system; and set memory access privileges of the second and third memory addresses to prevent at least one of a read, a write, or an execution access for the second and third memory addresses.

公开(公告)号：US11422943B2

公开(公告)日：2022-08-23

申请号：US15553853

申请日：2015-03-27

Applicant: Intel Corporation

Inventor： Jianhui Li ,  Yong Wu ,  Yihua Jin ,  Xueliang Zhong ,  Xiao Lin

IPC: G06F12/10 ,  G06F9/455 ,  G06F9/355 ,  G06F9/30

Abstract: One embodiment provides a device. The device includes a processor; a memory; and translator logic. The processor is to execute a host instruction set. The translator logic is to determine whether an offset is a constant and whether the offset is greater than zero and less than a maximum offset in response to receiving a guest memory access instruction that contains a base address plus or minus the offset, the maximum offset related to at least one of a host instruction set architecture (ISA) and a guest ISA.

公开(公告)号：US20160350161A1

公开(公告)日：2016-12-01

申请号：US14724394

申请日：2015-05-28

Applicant: Intel Corporation

Inventor： Yihua Jin ,  Xiao Dong Lin ,  Yong Wu ,  Jianhui Li ,  Xueliang Zhong

IPC: G06F9/54 ,  G06F12/08 ,  G06F9/46 ,  G06F12/02

CPC classification number: G06F9/54 ,  G06F9/461 ,  G06F9/466 ,  G06F12/0284 ,  G06F12/0842 ,  G06F2212/1044 ,  G06F2212/283 ,  G06F2212/608 ,  G06F2212/62

Abstract: Apparatuses, methods and storage media associated with multiple processor modes execution are described herein. In embodiments, an apparatus may include a processor with a plurality of processor modes, including a first processor mode to address a first address space, and a second processor mode to address a second address space, the second address space including the first address space. The apparatus may further include a signal handler to handle a signal from a kernel, in the first processor mode; and a signal handler wrapper to switch the processor to the second processor mode on delivery of the signal from the kernel, save a current extra context of the second processor mode from the second register file to a user stack, switch the processor back to the first processor mode, then invoke the signal handler to handle the signal. Other embodiments may be described or claimed.

Abstract translation: 这里描述了与多个处理器模式执行相关联的装置，方法和存储介质。 在实施例中，装置可以包括具有多个处理器模式的处理器，包括用于寻址第一地址空间的第一处理器模式和用于寻址第二地址空间的第二处理器模式，所述第二地址空间包括第一地址空间。 该装置还可以包括处理来自内核的信号的信号处理器，处于第一处理器模式; 以及信号处理器包装器，用于在从内核传递信号时将处理器切换到第二处理器模式，将第二处理器模式的当前额外上下文从第二寄存器文件保存到用户堆栈，将处理器切换回第一 处理器模式，然后调用信号处理程序来处理信号。 可以描述或要求保护其他实施例。

公开(公告)号：US08768682B2

公开(公告)日：2014-07-01

申请号：US13745203

申请日：2013-01-18

Applicant: Intel Corporation

Inventor： Yong Wu ,  Jianhui Li ,  Xiaodong Lin

IPC: G06F9/455 ,  G06F9/44

CPC classification number: G06F9/45504 ,  G06F9/455 ,  G06F9/45508 ,  G06F9/541

Abstract: Methods, apparatuses and storage medium associated with ISA bridging with support for virtual functions, are disclosed. In embodiments, at least one computer-readable storage medium may include instructions configured to enable a target device with a target ISA, in response to execution, to provide an ISA bridging layer to the target device to facilitate a library service of a library of the target device to call a virtual function of the library, while servicing an application operating on the target device, where the application has an overriding implementation. The ISA bridging layer may include a loader configured to load the application for execution, and as part of loading the application, detect the virtual function and modify a virtual function table of the application to enable the call. Other embodiments may be disclosed or claimed.

Abstract translation: 公开了与支持虚拟功能的ISA桥接相关联的方法，装置和存储介质。 在实施例中，至少一个计算机可读存储介质可以包括被配置为使得具有目标ISA的目标设备响应于执行而向目标设备提供ISA桥接层以促进图书馆服务 目标设备调用库的虚拟功能，同时为在目标设备上运行的应用程序提供服务，其中应用程序具有重写的实现。 ISA桥接层可以包括被配置为加载应用以执行的加载器，并且作为加载应用的一部分，检测虚拟功能并修改应用的虚拟功能表以启用该呼叫。 可以公开或要求保护其他实施例。