Slot negotiation method and device
    12.
    发明授权

    公开(公告)号:US12047165B2

    公开(公告)日:2024-07-23

    申请号:US17692810

    申请日:2022-03-11

    CPC classification number: H04J3/1658 H04J14/0227 H04J2203/0085

    Abstract: This application relates to a slot negotiation method and a device. The method includes: A transmitter sends a first FlexE overhead frame to a receiver, to request active/standby calendar switching. When the receiver is in a restart state, the receiver does not respond to the received first FlexE overhead frame. In addition, the RX sends a routine update second FlexE overhead frame to the transmitter. Determining that the second FlexE overhead frame is not a response to the first FlexE overhead frame, the transmitter sends a third FlexE overhead frame to request active/standby calendar switching again. According to the method in this application, incorrect calendar switching on the transmitter side caused by a mistaken response of the receiver can be avoided. This reduces the likelihood of a service interruption caused by the existing slot negotiation mechanism.

    Auto-negotiation method and apparatus

    公开(公告)号:US11949766B2

    公开(公告)日:2024-04-02

    申请号:US17721702

    申请日:2022-04-15

    Inventor: Xiang He Jun Hu

    CPC classification number: H04L69/24 H04L1/0072 H04L1/0076

    Abstract: An interface obtains basic page information from another interface. The basic page information includes N bits, the N bits include an FEC function indicator bit sequence including an FEC ability indicator bit and an FEC requested indicator bit. The interface determines, based on values of a plurality of bits in the N bits, an operation mode supported by the another interface. The FEC function indicator bit sequence includes a first FEC function indicator bit corresponding to m FEC abilities; or the FEC function indicator bit sequence includes a first FEC ability indicator bit corresponding to n FEC abilities, where both m and n are greater than or equal to 1. Because one FEC function indicator bit indicates more FEC abilities, N bits in a basic page can carry more information, so that a process of increasing auto-negotiation pages is slowed down, thereby avoiding impact on auto-negotiation efficiency.

    Data Stream Processing Method and Apparatus

    公开(公告)号:US20220294603A1

    公开(公告)日:2022-09-15

    申请号:US17831123

    申请日:2022-06-02

    Inventor: Weijun Le Xiang He

    Abstract: A method includes periodically inserting another AM into a data stream (DS) to obtain a second DS, and the first data stream includes a first alignment marker (AM); sending the second DS through physical lanes (PLs), where a quantity of the PLs is not equal to 2n, where the second AM's insertion period and each second AM's size is based on condition 1 or 2, where condition 1 is the quantity of the PLs, where condition 2 is condition 1 and a ratio of the second DS's rate to the first DS's rate, the second AM's insertion period and each second AM's size is an integer multiple of the quantity of the PLs, and where the second DS's rate is not less than the first DS's rate, and traffic per unit time corresponding to the rate of the second DS is an integer multiple of the quantity of the PLs.

    AUTO-NEGOTIATION METHOD AND APPARATUS

    公开(公告)号:US20220263600A1

    公开(公告)日:2022-08-18

    申请号:US17721702

    申请日:2022-04-15

    Inventor: Xiang He Jun Hu

    Abstract: An interface obtains basic page information from another interface. The basic page information includes N bits, the N bits include an FEC function indicator bit sequence including an FEC ability indicator bit and an FEC requested indicator bit. The interface determines, based on values of a plurality of bits in the N bits, an operation mode supported by the another interface. The FEC function indicator bit sequence includes a first FEC function indicator bit corresponding to m FEC abilities; or the FEC function indicator bit sequence includes a first FEC ability indicator bit corresponding to n FEC abilities, where both m and n are greater than or equal to 1. Because one FEC function indicator bit indicates more FEC abilities, N bits in a basic page can carry more information, so that a process of increasing auto-negotiation pages is slowed down, thereby avoiding impact on auto-negotiation efficiency.

    Method and apparatus for sending and receiving clock synchronization packet

    公开(公告)号:US11356188B2

    公开(公告)日:2022-06-07

    申请号:US16847258

    申请日:2020-04-13

    Abstract: This application provides a method for sending and receiving a clock synchronization packet in FlexE. The method includes: generating, by a sending apparatus, indication information and a plurality of data blocks, where the plurality of data blocks are obtained by encoding a first clock synchronization packet, the indication information is used to indicate a first data block, and the first data block is a data block used for timestamp sampling in the plurality of data blocks; determining, by the sending apparatus, according to the indication information, a moment at which the first data block arrives at a medium dependent interface MDI of the sending apparatus, and generating a sending timestamp, where the sending timestamp is used to record a sending moment of the first clock synchronization packet; generating a second clock synchronization packet carrying the sending timestamp; and sending, by the sending apparatus, the second clock synchronization packet.

    Data Transmission Method, Encoding Method, Decoding Method, Apparatus, Device, and Storage Medium

    公开(公告)号:US20220077875A1

    公开(公告)日:2022-03-10

    申请号:US17525189

    申请日:2021-11-12

    Abstract: A method includes: a first chip receives a first data stream from a second chip, where the first data stream is obtained through encoding by using a first forward error correction (FEC) code type; and the first chip re-encodes the first data stream at least once, to obtain a second data stream, where the second data stream is a concatenated FEC code stream obtained through encoding by using at least the first FEC code type and a second FEC code type. This application provides a concatenated coding scheme, so that a gain is higher, an FEC code type conversion process is simplified, a delay and device power consumption that are required during FEC code type conversion are reduced, and a data transmission distance and a data transmission rate are increased.

    Codeword Synchronization Method, Communication Device, Chip, and Chip System

    公开(公告)号:US20240388417A1

    公开(公告)日:2024-11-21

    申请号:US18787001

    申请日:2024-07-29

    Abstract: This application provides a codeword synchronization method, a communication device, a chip, and a chip system, and pertains to the field of communication technologies. The method includes: entering a synchronization position determining state in response to a start signal; determining a synchronization position in a received data sequence in the synchronization position determining state, where the synchronization position indicates a start position of a codeword in the data sequence; entering a loss-of-lock detection state in response to determining the synchronization position; and verifying, in the loss-of-lock detection state, a plurality of codewords selected based on the synchronization position, and re-entering the synchronization position determining state in response to a verification failure. According to the solutions of this application, codeword synchronization can be continuously implemented without inserting an additional alignment marker, thereby saving transmission resources.

Patent Agency Ranking