Memory activation method and apparatus, and memory controller

    公开(公告)号:US10127955B2

    公开(公告)日:2018-11-13

    申请号:US15607360

    申请日:2017-05-26

    Abstract: A first memory access request is obtained, where the first memory access request is used to request to access a first sub-row in a memory. A to-be-scheduled queue of the memory is searched for a second memory access request, where the to-be-scheduled queue of the memory includes multiple memory access requests, the second memory access request is used to request to access a second sub-row in the memory. The first sub-row and the second sub-row are located in a same row in the memory. The first memory access request and the second memory access request are combined to generate a first activation instruction, where the first activation instruction is used to instruct to activate the first sub-row and the second sub-row in the memory. The first activation instruction is sent to the memory.

    STORAGE UNIT, MEMORY, AND METHOD FOR CONTROLLING STORAGE UNIT
    13.
    发明申请
    STORAGE UNIT, MEMORY, AND METHOD FOR CONTROLLING STORAGE UNIT 有权
    存储单元,存储器和用于控制存储单元的方法

    公开(公告)号:US20160231959A1

    公开(公告)日:2016-08-11

    申请号:US15133897

    申请日:2016-04-20

    Abstract: A storage unit includes a U-shaped magnetic track, a first drive circuit, a second drive circuit, a first drive port, and a second drive port. The U-shaped magnetic track includes a first port, a second port, a first storage area, and a second storage area. By controlling input voltages of the first port, the second port, the first drive port, and the second drive port and driving the first drive circuit, a current pulse is generated in the first storage area, and a magnetic domain wall in the first storage area is driven to move. By controlling the input voltages of the first port, the second port, the first drive port, and the second drive port and driving the second drive circuit, a current pulse is generated in the second storage area, and a magnetic domain in the second storage area is driven to move.

    Abstract translation: 存储单元包括U形磁迹,第一驱动电路,第二驱动电路,第一驱动端口和第二驱动端口。 U形磁道包括第一端口,第二端口,第一存储区域和第二存储区域。 通过控制第一端口,第二端口,第一驱动端口和第二驱动端口的输入电压并驱动第一驱动电路,在第一存储区域中产生电流脉冲,并且在第一存储器中产生磁畴壁 区域被驱动移动。 通过控制第一端口,第二端口,第一驱动端口和第二驱动端口的输入电压并驱动第二驱动电路,在第二存储区域中产生电流脉冲,并且在第二存储器中产生磁畴 区域被驱动移动。

    Information writing method and apparatus

    公开(公告)号:US11853608B2

    公开(公告)日:2023-12-26

    申请号:US17559478

    申请日:2021-12-22

    Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.

    Information writing method and apparatus

    公开(公告)号:US11237762B2

    公开(公告)日:2022-02-01

    申请号:US16805192

    申请日:2020-02-28

    Abstract: An information writing method is applied to an non-volatile dual in-line memory module (NVDIMM), the NVDIMM includes an NVDIMM controller and a non-volatile memory (NVM), and the method includes receiving, by the NVDIMM controller, a sanitize command from a host, where the sanitize command is used to instruct the NVDIMM controller to sanitize data in the NVM using a first write pattern, and the first write pattern is one of at least two patterns of writing information into the NVM, and writing, by the NVDIMM controller, information into the NVM according to the sanitize command.

    Memory access technology and computer system

    公开(公告)号:US11231864B2

    公开(公告)日:2022-01-25

    申请号:US16927066

    申请日:2020-07-13

    Abstract: A computer system includes a memory controller and a non-volatile dual in-line memory module (NVDIMM) connected to the memory controller. The NVDIMM comprises a non-volatile memory (NVM) for storing data and a media controller. After receiving a read command for reading first data stored in the NVDIMM from the memory controller, the media controller reads multiple data subblocks of the first data from the NVM. After sending multiple ready signals to notify the memory controller that multiple data subblocks of the first data are available, the media controller receives multiple send commands for fetching the multiple data subblocks. The media controller then transmits to the memory controller the multiple data subblocks in response to the multiple send commands.

    Recording method, recording play method, apparatuses, and terminals

    公开(公告)号:US10834503B2

    公开(公告)日:2020-11-10

    申请号:US16812813

    申请日:2020-03-09

    Abstract: A recording play method, terminal and non-transitory computer-readable storage medium are provided, where the recording play method includes obtaining a recording file, wherein the recording file comprises saved recording data in all sound source directions via the at least three microphones; receiving a first gesture on an interface displayed on the screen, wherein the first gesture indicates a first recording play direction; determining, according to the first gesture, a first recording data matching the first recording play direction from the saved recording data in all sound source directions; and playing the first recording data matching the first recording play direction.

    Memory Access Technology
    20.
    发明申请

    公开(公告)号:US20190272122A1

    公开(公告)日:2019-09-05

    申请号:US16414383

    申请日:2019-05-16

    Abstract: A memory access technology applied to a computer system includes a first-level memory, a second-level memory, and a memory controller. The first-level memory is configured to cache data in the second-level memory. A plurality of access requests for accessing different memory blocks has a mapping relationship with a first cache line in the first-level memory, and the memory controller compares tags of the plurality of access requests with a tag of the first cache line in a centralized manner to determine whether the plurality of access requests hit the first-level memory.

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