公开(公告)号：US11973856B2

公开(公告)日：2024-04-30

申请号：US17321707

申请日：2021-05-17

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao Li ,  Fei Luo ,  Jiankang Li ,  Jiang Zhu ,  Jieping Zeng

IPC: H04L7/00 ,  G06F13/42

CPC classification number: H04L7/005 ,  G06F13/4265 ,  G06F2213/0026 ,  G06F2213/0042

Abstract: This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

公开(公告)号：US20240097947A1

公开(公告)日：2024-03-21

申请号：US18521508

申请日：2023-11-28

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Shibin Xu ,  Kejian Wang ,  Fei Luo ,  Jiankang Li

IPC: H04L25/03 ,  H04L1/00

CPC classification number: H04L25/03343 ,  H04L1/0023 ,  H04L1/0033

Abstract: Embodiments of this application disclose a data interface equalization adjustment method and apparatus, a device, and a storage medium, and relate to the field of data interface technologies. The method includes: A second device determines equalization parameter indication information of a first transmitter TX on a first data interface. The second device sends a first equalization training sequence block ETSB to a corresponding RX on the first data interface through a TX on a second data interface, where the first ETSB carries the equalization parameter indication information and equalization target indication information, and the equalization target indication information indicates that the first TX is an equalization target. The first device determines the equalization target to be the first TX based on the equalization target indication information, and adjusts an equalization parameter of the first TX to an equalization parameter indicated by the equalization parameter indication information.

公开(公告)号：US11799697B2

公开(公告)日：2023-10-24

申请号：US17959490

申请日：2022-10-04

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao Li ,  Fei Luo ,  Er Nie

IPC: H04L25/03 ,  G06F13/42 ,  H04B1/38

CPC classification number: H04L25/03012 ,  G06F13/4282 ,  H04B1/38 ,  G06F2213/0026

Abstract: A fast equalization method is provided, which includes: storing a receive parameter and a transmit parameter, of each of a primary chip and a secondary chip, that meet a link stability requirement and that are obtained when link equalization is previously performed; and when determining that link equalization needs to be performed, configuring, as first fast equalization timeout duration, a larger value in initial fast equalization timeout duration of the primary chip and initial fast equalization timeout duration of the secondary chip, and invoking the foregoing receive and transmit parameters, so that the primary chip and the secondary chip perform a current time of link equalization based on the first fast equalization timeout duration and the foregoing transmit and receive parameters.

公开(公告)号：US12095597B2

公开(公告)日：2024-09-17

申请号：US18070986

申请日：2022-11-29

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongyao Li ,  Fei Luo ,  Jiang Zhu

IPC: H04L25/03

CPC classification number: H04L25/03885

Abstract: An equalization training method and apparatus are described. The method includes obtaining a training rate of each of a master chip and a slave chip in a target phase of equalization training. The method also includes determining a target rate threshold interval within which the training rate in the target phase falls, determining, based on a correspondence between N+1 rate threshold intervals and N+1 equalization timeout periods, a target equalization timeout period corresponding to the target rate threshold interval, and configuring the target equalization timeout period as an equalization timeout period in the target phase. According to this method, an equalization timeout period used for equalization training can be flexibly configured for each equalization training process, so that the configured equalization timeout period better conforms to a training rate currently used for link negotiation, to better ensure that an equalization parameter is found within the configured equalization timeout period, thereby improving an equalization training success rate.

公开(公告)号：US20230124534A1

公开(公告)日：2023-04-20

申请号：US18083694

申请日：2022-12-19

Applicant: HUAWEI TECHNOLOGIES CO., LTD.

Inventor： Yongchen Jin ,  Fei Luo ,  Guoyu Wang ,  Ming Chen ,  Yinzhong Tang

IPC: G11B33/04

Abstract: A storage device includes a hard disk backplane, a first cascading board, and a hard disk array. The hard disk array includes a plurality of hard disks, and is located on a first side of the hard disk backplane. The first cascading board is a field-replaceable unit FRU, and is located on a second side of the hard disk backplane.

公开(公告)号：US10958413B2

公开(公告)日：2021-03-23

申请号：US16533365

申请日：2019-08-06

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongyao Li ,  Jiankang Li ,  Jun Yu ,  Jiang Zhu ,  Fei Luo

IPC: H03H7/30 ,  H04L7/033 ,  H04L1/00 ,  H04L7/00 ,  H04L25/03 ,  H04L29/06

Abstract: A retimer is provided. The retimer includes: a data channel circuit, configured to implement, under a function of a current phase locked loop, equalization processing-based transparent transmission of a signal between a first communications device and a second communications device; and the link adjustment circuit, configured to: when determining, based on link status information of the data channel circuit, that a rate of a link needs to be changed, configure an operating parameter of a target phase locked loop as an operating parameter corresponding to a changed rate; and switch the currently used phase locked loop to the target phase locked loop when detecting that the link enters a rate-changing state, where the data channel circuit is further configured to implement, under a function of the target phase locked loop, the transparent transmission of a signal between the first communications device and the second communications device.