公开(公告)号：US20150213107A1

公开(公告)日：2015-07-30

申请号：US14595138

申请日：2015-01-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Kyoung Hyun PARK ,  Mai Hai THANH ,  Hun Soon LEE ,  Chang Soo KIM ,  Mi Young LEE

IPC: G06F17/30

CPC classification number: G06F16/2365

Abstract: An apparatus of managing data according to the present invention includes a query processor, a page monitor, a page layout manager and a data storage manager. The query processor processes a user query. At the time of processing the user query, the page monitor collects accessed column information and selectivity information of accessed columns from the query processor and collects access page information from a data storage manager to create page monitoring information. The page layout manager creates page column group information by grouping columns adjacent to each other for each page at a predetermined time interval based on the page monitoring information. The data storage manager stores data in a main memory by reconfiguring a page based on the page column group information for a candidate page of which an access frequency is greater than a predetermined access frequency based on the page monitoring information.

Abstract translation: 根据本发明的管理数据的装置包括查询处理器，页面监视器，页面布局管理器和数据存储管理器。 查询处理器处理用户查询。 在处理用户查询时，页面监视器从查询处理器收集所访问列的访问列信息和选择性信息，并从数据存储管理器收集访问页面信息以创建页面监视信息。 页面布局管理器基于页面监视信息以预定的时间间隔对每个页面彼此相邻的列进行分组来创建页面列组信息。 数据存储管理器基于页面监视信息，基于用于访问频率大于预定访问频率的候选页面的页面列组信息重新配置页面来将数据存储在主存储器中。

公开(公告)号：US20210303982A1

公开(公告)日：2021-09-30

申请号：US17205433

申请日：2021-03-18

Applicant: Electronics and Telecommunications Research Institute

Inventor： Mi Young LEE ,  Young-deuk JEON ,  Byung Jo KIM ,  Ju-Yeob KIM ,  Jin Kyu KIM ,  Ki Hyuk PARK ,  JOO HYUN LEE ,  MIN-HYUNG CHO

IPC: G06N3/063 ,  G06F7/544 ,  G06N3/08

Abstract: Disclosed is a neural network computing device. The neural network computing device includes a neural network accelerator including an analog MAC, a controller controlling the neural network accelerator in one of a first mode and a second mode, and a calibrator that calibrating a gain and a DC offset of the analog MAC. The calibrator includes a memory storing weight data, calibration weight data, and calibration input data, a gain and offset calculator reading the calibration weight data and the calibration input data from the memory, inputting the calibration weight data and the calibration input data to the analog MAC, receiving calibration output data from the analog MAC, and calculating the gain and the DC offset of the analog MAC, and an on-device quantizer reading the weight data, receiving the gain and the DC offset, generating quantized weight data, based on the gain and the DC offset.

公开(公告)号：US20200226456A1

公开(公告)日：2020-07-16

申请号：US16742808

申请日：2020-01-14

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Young-deuk JEON ,  Byung Jo KIM ,  Ju-Yeob KIM ,  Jin Kyu KIM ,  Ki Hyuk PARK ,  Mi Young LEE ,  Joo Hyun LEE ,  Min-Hyung CHO

IPC: G06N3/063 ,  G06F17/15 ,  G06F7/575

Abstract: The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.

公开(公告)号：US20180225563A1

公开(公告)日：2018-08-09

申请号：US15868889

申请日：2018-01-11

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ju-Yeob KIM ,  Byung Jo KIM ,  Jin Kyu KIM ,  Mi Young LEE ,  Seong Min KIM ,  Joo Hyun LEE

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/049 ,  G06N3/063 ,  G06N3/08

Abstract: Provided is an artificial neural network device including pre-synaptic neurons configured to generate a plurality of input spike signals, and a post-synaptic neuron configured to receive the plurality of input spike signals and to generate an output spike signal during a plurality of time periods, wherein the post-synaptic neuron respectively applies different weights in the plurality of time periods according to contiguousness with a reference time period in which input spike signals, which lead generation of the output spike signal from among the plurality of input spike signals, are received.

公开(公告)号：US20180197084A1

公开(公告)日：2018-07-12

申请号：US15866351

申请日：2018-01-09

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Ju-Yeob KIM ,  Byung Jo KIM ,  Jin Kyu KIM ,  Mi Young LEE ,  Seong Min KIM ,  Joo Hyun LEE

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/084 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063

Abstract: Provided is a convolutional neural network system. The system includes an input buffer configured to store an input feature, a parameter buffer configured to store a learning parameter, a calculation unit configured to perform a convolution layer calculation or a fully connected layer calculation by using the input feature provided from the input buffer and the learning parameter provided from the parameter buffer, and an output buffer configured to store an output feature outputted from the calculation unit and output the stored output feature to the outside. The parameter buffer provides a real learning parameter to the calculation unit at the time of the convolution layer calculation and provides a binary learning parameter to the calculation unit at the time of the fully connected layer calculation.

公开(公告)号：US20180131946A1

公开(公告)日：2018-05-10

申请号：US15806200

申请日：2017-11-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Mi Young LEE ,  Byung Jo KIM ,  Ju-Yeob KIM ,  Jin Kyu KIM ,  Seong Min KIM ,  Joo Hyun LEE

IPC: H04N19/169 ,  G06F17/30 ,  G06N3/08 ,  G06N3/063 ,  H04N19/13 ,  G06K9/62

CPC classification number: H04N19/169 ,  G06F16/50 ,  G06K9/6256 ,  G06K9/6267 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/08 ,  H04N19/13 ,  H04N19/48

Abstract: Provided is a convolution neural network system including an image database configured to store first image data, a machine learning device configured to receive the first image data from the image database and generate synapse data of a convolution neural network including a plurality of layers for image identification based on the first image data, a synapse data compressor configured to compress the synapse data based on sparsity of the synapse data, and an image identification device configured to store the compressed synapse data and perform image identification on second image data without decompression of the compressed synapse data.

公开(公告)号：US20180129935A1

公开(公告)日：2018-05-10

申请号：US15806111

申请日：2017-11-07

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jin Kyu KIM ,  Byung Jo KIM ,  Seong Min KIM ,  Ju-Yeob KIM ,  Mi Young LEE ,  Joo Hyun LEE

IPC: G06N3/063 ,  G06N3/04 ,  G06F7/544

CPC classification number: G06N3/063 ,  G06F7/5443 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/082

Abstract: Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiply-accumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.