公开(公告)号：US09425743B2

公开(公告)日：2016-08-23

申请号：US14565939

申请日：2014-12-10

Applicant: Electronics and Telecommunications Research Institute

Inventor： Young Ho Kim ,  Sang Soo Lee

IPC: H03F3/45 ,  H03F1/02 ,  H03F1/56 ,  H03F1/32 ,  H03F1/08

CPC classification number: H03F1/0205 ,  H03F1/086 ,  H03F1/3205 ,  H03F1/3211 ,  H03F1/56 ,  H03F3/45183 ,  H03F3/45197 ,  H03F3/45748 ,  H03F2200/387 ,  H03F2200/405 ,  H03F2200/453 ,  H03F2203/45112 ,  H03F2203/45296 ,  H03F2203/45301 ,  H03F2203/45374 ,  H03F2203/45644 ,  H03F2203/45652 ,  H03F2203/45702

Abstract: Provided is a buffer amplifier. The buffer amplifier includes: a replica bias unit dividing an internal power voltage received from an internal power node to generate a bias voltage; an input unit including a first differential amplifier comparing a first differential input signal with the bias voltage to output a first internal signal and a second differential amplifier comparing a second differential input signal with the bias voltage to output a second internal signal; and an output unit including a third differential amplifier comparing the first internal signal with the second internal signal to output a first differential output signal and a second differential output signal.

Abstract translation: 提供了一个缓冲放大器。 缓冲放大器包括：复制偏置单元，分割从内部功率节点接收的内部电力电压以产生偏置电压; 输入单元，包括：第一差分放大器，将第一差分输入信号与偏置电压进行比较以输出第一内部信号;以及第二差分放大器，将第二差分输入信号与偏置电压进行比较，以输出第二内部信号; 以及输出单元，其包括将所述第一内部信号与所述第二内部信号进行比较的第三差分放大器，以输出第一差分输出信号和第二差分输出信号。

公开(公告)号：US08683397B2

公开(公告)日：2014-03-25

申请号：US13674281

申请日：2012-11-12

Applicant: Electronics and Telecommunications Research Institute

Inventor： Soon Il Yeo ,  Young Ho Kim

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/66 ,  G06F2217/82

Abstract: Disclosed are a method and an apparatus of designing a semiconductor chip. The disclosed method includes the steps of: storing a plurality of EMS (Electro Magnetic Susceptibility) semiconductor IPs (Intellectual Property) and a plurality of EMI (Electro Magnetic Interference) semiconductor IPs; selecting a proper semiconductor IP from among the plurality of EMS shielding semiconductor IPs in a case of an input pin, and selecting a proper semiconductor IP from among the plurality of EMI shielding semiconductor IPs in a case of an output pin; and designing the semiconductor chip by disposing the selected semiconductor IP.

Abstract translation: 公开了一种设计半导体芯片的方法和设备。 所公开的方法包括以下步骤：存储多个EMS（电磁敏感性）半导体IP（知识产权）和多个EMI（电磁干扰）半导体IP; 在输入引脚的情况下，从多个EMS屏蔽半导体IP中选择适当的半导体IP，并且在输出引脚的情况下从多个EMI屏蔽半导体IP中选择合适的半导体IP; 以及通过配置所选择的半导体IP来设计半导体芯片。