公开(公告)号：US10014401B2

公开(公告)日：2018-07-03

申请号：US15414156

申请日：2017-01-24

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jeho Na ,  Hyung Seok Lee ,  Chi Hoon Jun ,  Sang Choon Ko ,  Myungjoon Kwack ,  Young Rak Park ,  Woojin Chang ,  Hyun-Gyu Jang ,  Dong Yun Jung

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L23/31 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7787 ,  H01L23/315 ,  H01L23/3171 ,  H01L23/3178 ,  H01L23/3192 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/41758 ,  H01L29/42364 ,  H01L29/42372 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device includes a semiconductor structure including a substrate, a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer, a first passivation pattern provided on the semiconductor structure, and first and second conductive patterns provided on the semiconductor structure and spaced from the first passivation pattern.

公开(公告)号：US09337121B2

公开(公告)日：2016-05-10

申请号：US14324724

申请日：2014-07-07

Applicant: Electronics and Telecommunications Research Institute

Inventor： Chi Hoon Jun ,  Sang Choon Ko ,  Seok-Hwan Moon ,  Woojin Chang ,  Sung-Bum Bae ,  Young Rak Park ,  Je Ho Na ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L23/367 ,  H01L21/308 ,  H01L23/473 ,  H01L23/467 ,  H01L21/3065 ,  H01L21/3205

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes: an active region provided on a substrate; an inlet channel formed as a single cavity buried in one side of the substrate; an outlet channel formed as a single cavity buried in the other side of the substrate; a micro channel array comprising a plurality of micro channels, wherein the plurality of micro channels are formed as a plurality of cavities buried in the substrate, and one end of the micro channel array is connected to a side of the inlet channel and the other end of the micro channel array is connected to a side of the outlet channel; and a micro heat sink array separating the micro channels from one another.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。

公开(公告)号：US08901608B2

公开(公告)日：2014-12-02

申请号：US13908076

申请日：2013-06-03

Applicant: Electronics and Telecommunications Research Institute

Inventor： Jong-Won Lim ,  Hokyun Ahn ,  Woojin Chang ,  Dong Min Kang ,  Seong-Il Kim ,  Sang-Heung Lee ,  Hyung Sup Yoon ,  Chull Won Ju ,  Hae Cheon Kim ,  Jae Kyoung Mun ,  Eun Soo Nam

IPC: H01L33/00 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/778 ,  H01L29/402 ,  H01L29/42316 ,  H01L29/66431

Abstract: A high electron mobility transistor includes a T-type gate electrode disposed on a substrate between source and drain electrodes and insulating layers disposed between the substrate and the T-type gate electrode. The insulating layers include first, second, and third insulating layers. The third insulating layer is disposed between the substrate and a head portion of the T-type gate electrode such that a portion of the third insulating layer is in contact with a foot portion of the T-type gate electrode. The second insulating layer is disposed between the substrate and the head portion of the T-type gate electrode to be in contact with the third insulating layer. The first insulating layer and another portion of the third insulating layer are sequentially stacked between the substrate and the head portion of the T-type gate electrode to be in contact with the second insulating layer.

Abstract translation: 高电子迁移率晶体管包括设置在源极和漏极之间的衬底上的T型栅电极和设置在衬底和T型栅电极之间的绝缘层。 绝缘层包括第一绝缘层，第二绝缘层和第三绝缘层。 第三绝缘层设置在基板和T型栅电极的头部之间，使得第三绝缘层的一部分与T型栅极的脚部接触。 第二绝缘层设置在基板与T型栅电极的头部之间以与第三绝缘层接触。 所述第一绝缘层和所述第三绝缘层的另一部分依次层叠在所述基板与所述T型栅电极的头部之间，以与所述第二绝缘层接触。