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    Methods and apparatus for testing and repairing digital memory circuits
    11.
    发明授权
    Methods and apparatus for testing and repairing digital memory circuits 有权
    用于测试和修复数字存储器电路的方法和装置

    公开(公告)号：US09165687B2

    公开(公告)日：2015-10-20

    申请号：US14160542

    申请日：2014-01-21

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Shadab Nazar ,  Sanjeev Joshi

    IPC: G11C29/00 ,  G11C29/08 ,  G11C29/56 ,  G11C29/04

    CPC classification number: G11C29/12 ,  G11C29/08 ,  G11C29/56008 ,  G11C29/70 ,  G11C2029/0401 ,  G11C2029/0409

    Abstract: An ActiveTest solution for memory is disclosed which can search for memory errors during the operation of a product containing digital memory. The ActiveTest system tests memory banks that are not being accessed by normal memory users in order to continually test the memory system in the background. When there is a conflict between the ActiveTest system and a memory user, the memory user is generally given priority.

    Abstract translation: 公开了用于存储器的ActiveTest解决方案，其可以在包含数字存储器的产品的操作期间搜索存储器错误。 ActiveTest系统测试正常内存用户未被访问的内存块，以便在后台持续测试内存系统。 当ActiveTest系统和内存用户之间存在冲突时，内存用户通常被优先考虑。

    SHIM LAYER FOR EXTRACTING AND PRIORITIZING UNDERLYING RULES FOR MODELING NETWORK INTENTS
    14.
    发明申请
    SHIM LAYER FOR EXTRACTING AND PRIORITIZING UNDERLYING RULES FOR MODELING NETWORK INTENTS 有权

    公开(公告)号：US20210144069A1

    公开(公告)日：2021-05-13

    申请号：US17153831

    申请日：2021-01-20

    Applicant: Cisco Technology, Inc.

    Inventor： Advait Dixit ,  Ramana Rao Kompella ,  Kartik Mohanram ,  Sundar Iyer ,  Shadab Nazar ,  Chandra Nagarajan

    IPC: H04L12/24

    Abstract: Systems, methods, and computer-readable media for receiving one or more models of network intents, comprising a plurality of contracts between providers and consumers, each contract containing entries with priority values. Each contract is flattened into a listing of rules and a new priority value is calculated. The listing of rules encodes the implementation of the contract between the providers and the consumers. Each entry is iterated over and added to a listing of entries if it is not already present. For each rule, the one or more entries associated with the contract from which the rule was flattened are identified, and for each given entry a flat rule comprising the combination of the rule and the entry is generated, wherein a flattened priority is calculated based at least in part on the priority value of the given one of given entry and the priority value of the rule.

    TOPOLOGY EXPLORER
    15.
    发明申请
    TOPOLOGY EXPLORER 审中-公开

    公开(公告)号：US20200099589A1

    公开(公告)日：2020-03-26

    申请号：US16698387

    申请日：2019-11-27

    Applicant: Cisco Technology, Inc.

    Inventor： Divjyot Sethi ,  Chandra Nagarajan ,  Ramana Rao Kompella ,  Gaurav Gupta ,  Sundar Iyer

    IPC: H04L12/24 ,  H04L12/26

    Abstract: Systems, methods, and computer-readable media for discovering a network's topology and health. In some examples, a system can obtain, from at least one of a plurality of controllers on a network, a logical model of the network, the logical model including configurations of one or more objects defined for the network. Based on the logical model, the system can identify a respective location of the plurality of controllers in the network and a plurality of nodes in a fabric of the network. Based on the respective location of the plurality of controllers and plurality of nodes, the system can poll the plurality of controllers and plurality of nodes for respective status information, and determine a health and topology of the network based on the logical model, the respective location, and respective status information.

    SEMANTIC ANALYSIS TO DETECT SHADOWING OF RULES IN A MODEL OF NETWORK INTENTS
    16.
    发明申请
    SEMANTIC ANALYSIS TO DETECT SHADOWING OF RULES IN A MODEL OF NETWORK INTENTS 审中-公开

    公开(公告)号：US20180351819A1

    公开(公告)日：2018-12-06

    申请号：US15693242

    申请日：2017-08-31

    Applicant: Cisco Technology, Inc.

    Inventor： Kartik Mohanram ,  Sundar Iyer ,  Ramana Rao Kompella ,  Navneet Yadav

    IPC: H04L12/24

    Abstract: Systems, methods, and computer-readable media for performing semantic analysis to identify shadowing events. One or more models of network intents, based at least in part on a priority-ordered listing of rules representing network intents, is received. Each rule comprises a Boolean function of one or more packet characteristics and network fabric conditions, and a corresponding network action. For each given rule of the priority-ordered listing of rules, partial and complete shadowing events are detected based on semantic analysis. The semantic analysis comprises calculating an inverse set that comprises the inverse of the set comprising all rules with a higher or equal priority to the given rule, and then calculating a shadowing parameter that comprises the intersection between the inverse set and the given rule. If the shadowing parameter is equal to zero, a complete shadowing event is detected. If the shadowing parameter is not equal to zero and is not equal to the given rule, a partial shadowing event is detected.

    NETWORK POLICY ANALYSIS FOR NETWORKS
    17.
    发明申请
    NETWORK POLICY ANALYSIS FOR NETWORKS 审中-公开

    公开(公告)号：US20180351791A1

    公开(公告)日：2018-12-06

    申请号：US15663233

    申请日：2017-07-28

    Applicant: Cisco Technology, Inc.

    Inventor： Chandra Nagarajan ,  Kartik Mohanram ,  Sundar Iyer ,  Ramana Rao Kompella

    IPC: H04L12/24 ,  H04L12/46 ,  H04L29/06

    CPC classification number: H04L41/08 ,  H04L12/4641 ,  H04L41/0873 ,  H04L41/0893 ,  H04L63/101 ,  H04L63/20

    Abstract: Systems, methods, and computer-readable media for performing network assurance in a traditional network. In some examples, a system can collect respective sets of configurations programmed at network devices in a network and, based on the respective sets of configurations, determine a network-wide configuration of the network, the network-wide configuration including virtual local area networks (VLANs), access control lists (ACLs) associated with the VLANs, subnets, and/or a topology. Based on the network-wide configuration of the network, the system can compare the ACLs for each of the VLANs to yield a VLAN consistency check, compare respective configurations of the subnets to yield a subnet consistency check, and perform a topology consistency check based on the topology. Based on the VLAN consistency check, the subnet consistency check, and the topology consistency check, the system can determine whether the respective sets of configurations programmed at the network devices contain a configuration error.

    ASSURANCE OF QUALITY-OF-SERVICE CONFIGURATIONS IN A NETWORK
    18.
    发明申请
    ASSURANCE OF QUALITY-OF-SERVICE CONFIGURATIONS IN A NETWORK 审中-公开

    公开(公告)号：US20180309640A1

    公开(公告)日：2018-10-25

    申请号：US15693299

    申请日：2017-08-31

    Applicant: Cisco Technology, Inc.

    Inventor： Chandra Nagarajan ,  Kartik Mohanram ,  Ramana Rao Kompella ,  Divjyot Sethi ,  Sundar Iyer

    IPC: H04L12/24

    Abstract: Systems, methods, and computer-readable media for assurance of quality-of-service configurations in a network. In some examples, a system obtains a logical model of a software-defined network, the logical model including rules specified for the software-defined network, the logical model being based on a schema defining manageable objects and object properties for the software-defined network. The system also obtains, for each node in the software-defined network, a respective hardware model, the respective hardware model including rules rendered at the node based on a respective node-specific representation of the logical model. Based on the logical model and the respective hardware model, the system can perform an equivalency check between the rules in the logical model and the rules in the respective hardware model to determine whether the logical model and the respective hardware model contain configuration inconsistencies.

    POLICY ASSURANCE FOR SERVICE CHAINING
    19.
    发明申请
    POLICY ASSURANCE FOR SERVICE CHAINING 审中-公开

    公开(公告)号：US20180309632A1

    公开(公告)日：2018-10-25

    申请号：US15693310

    申请日：2017-08-31

    Applicant: Cisco Technology, Inc.

    Inventor： Ramana Rao Kompella ,  Kartik Mohanram ,  Advait Dixit ,  Sundar Iyer

    IPC: H04L12/24

    CPC classification number: H04L41/0893 ,  H04L41/0806 ,  H04L41/0813 ,  H04L41/0853 ,  H04L41/0869 ,  H04L41/145 ,  H04L41/50

    Abstract: In some examples, a system obtains a network logical model and, for each node in a network, a node-level logical, concrete, and hardware model. The system identifies a service function chain, and determines a respective set of service function chain rules. For each node, the system determines whether the respective set of service function chain rules is correctly captured in the node-level logical model and/or concrete model to yield a node containment check result. Based on a comparison of policy actions in the concrete model, hardware model, and at least one of the node-level logical model or network logical model, the system determines whether the respective set of service function chain rules is correctly rendered on each node to yield a node rendering check result. Based on the node containment check result and node rendering check result, the system determines whether the service function chain is correctly configured.

    Hierarchical memory system compiler
    20.
    发明授权
    Hierarchical memory system compiler 有权

    公开(公告)号：US09678669B2

    公开(公告)日：2017-06-13

    申请号：US14083437

    申请日：2013-11-18

    Applicant: Cisco Technology, Inc.

    Inventor： Sundar Iyer ,  Sanjeev Joshi ,  Shang-Tse Chuang

    IPC: G06F17/50 ,  G06F9/455 ,  G06F3/06 ,  G06F12/0844 ,  G06F12/0846 ,  G06F12/0855

    CPC classification number: G06F3/0607 ,  G06F3/0629 ,  G06F3/0683 ,  G06F12/0844 ,  G06F12/0851 ,  G06F12/0855

    Abstract: Designing memory subsystems for integrated circuits can be time-consuming and costly task. To reduce development time and costs, an automated system and method for designing and constructing high-speed memory operations is disclosed. The automated system accepts a set of desired memory characteristics and then methodically selects different potential memory system design types and different implementations of each memory system design type. The potential memory system design types may include traditional memory systems, optimized traditional memory systems, intelligent memory systems, and hierarchical memory systems. A selected set of proposed memory systems that meet the specified set of desired memory characteristics is output to a circuit designer. When a circuit designer selects a proposed memory system, the automated system generates a complete memory system design, a model for the memory system, and a test suite for the memory system.

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