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11.发明申请公开(公告)号：US20190173028A1
公开(公告)日：2019-06-06
申请号：US15991134
申请日：2018-05-29
Inventor： Jun WANG , Guangyao LI , Dongfang WANG , Jun LIU , Guangcai YUAN , Leilei CHENG
Abstract: The present disclosure relates to a substrate, a method for fabricating the same and an organic light emitting diode display device. The substrate includes a metal foil. A metal material used for the metal foil is capable of being anodized and a plurality of concave light trapping microstructures is formed on a surface of the metal foil.
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公开(公告)号：US20250048871A1
公开(公告)日：2025-02-06
申请号：US18920115
申请日：2024-10-18
Inventor： Ning LIU , Dacheng ZHANG , Tong WU , Jun LIU , Qinghe WANG , Yang ZHANG , Bin ZHOU , Liangchen YAN , Huadong WANG , Chongchong LIU , Jie ZHANG
IPC: H10K59/131 , H10K59/12 , H10K71/20
Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, organic light-emitting elements, a data line, and an electrode line. The organic light-emitting element includes a first electrode, a light-emitting layer and a second electrode sequentially stacked; the data line is located between the base substrate and the organic light-emitting element; the electrode line is on the same layer as the data line and located in a region outside a light-emitting region of the organic light-emitting element. The display substrate further includes at least one connection portion, which is in the region outside the light-emitting region and is configured to connect the electrode line and the first electrode, the connection portion is spaced apart from the second electrode, and the light-emitting layer covers the second electrode and the at least one connection portion.
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公开(公告)号：US20220064783A1
公开(公告)日：2022-03-03
申请号：US17501383
申请日：2021-10-14
Inventor： Tongshang SU , Dongfang WANG , Leilei CHENG , Jun LIU , Ning LIU , Qinghe WANG , Liangchen YAN
Abstract: A sputtering system and a deposition method are provided. The sputtering system includes at least two sputtering chambers. Each of the at least two sputtering chambers includes a plurality of targets separated from each other and a plurality of target pedestals. Each of the plurality of targets is mounted on a corresponding target pedestal of the plurality of target pedestals, and a gap between two adjacent targets of the plurality of targets has a width sufficient to accommodate at least one of the plurality of targets.
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公开(公告)号：US20210313356A1
公开(公告)日：2021-10-07
申请号：US16761231
申请日：2019-10-28
Inventor： Ning LIU , Bin ZHOU , Jun LIU , Yang ZHANG , Tongshang SU , Haitao WANG
Abstract: The present disclosure provides a display substrate, a method for preparing the same, and a display device including the display substrate. The method includes: forming a conductive layer; forming a first photoresist pattern and a second photoresist pattern on the conductive layer, in which the adhesion between the first photoresist pattern and the conductive layer is less than the adhesion between the second photoresist pattern and the conductive layer; and etching the conductive layer by using the first photoresist pattern and the second photoresist pattern as masks to form a first conductive pattern and a second conductive pattern, respectively, in which a line width difference between the first conductive pattern and the first photoresist pattern is greater than a line width difference between the second conductive pattern and the second photoresist pattern.
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公开(公告)号：US20210296406A1
公开(公告)日：2021-09-23
申请号：US17264283
申请日：2020-05-12
Inventor： Jingang FANG , Luke DING , Jun LIU , Bin ZHOU , Jun CHENG
Abstract: The present disclosure relates to the technical field of display, and discloses an array substrate, a preparation method therefor, and a display device. When dielectric layers, such as a buffer layer, an interlayer dielectric layer, and a gate insulation layer, are formed between a source-drain electrode and a substrate, the thickness of at least one dielectric layer among said dielectric layers underneath a first through hole for connecting a drain electrode and an anode is increased, which is to say that the drain electrode is raised to be further away from the substrate, causing the drain electrode to be closer to a surface of a planarization layer that faces away from the substrate, i.e., reducing the thickness of a portion of the planarization layer above the drain electrode.
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Patent Agency Ranking
公开(公告)号：US20210267053A1
公开(公告)日：2021-08-26
申请号：US17183909
申请日：2021-02-24
Inventor： Yongchao HUANG , Qinghe WANG , Haitao WANG , Jun LIU , Jun CHENG , Ce ZHAO , Liangchen YAN
Abstract: The present disclosure provides a display substrate, a method for manufacturing the display substrate, and a display device. The display substrate includes a first conductive line extending in a first direction on a base substrate, a second conductive line extending in a second direction crossing the first direction on the base substrate, and an insulation layer arranged between the first conductive line and the second conductive line. The display substrate further includes a buffer layer arranged between the first conductive line and the base substrate, a groove extending in the first direction is formed in the buffer layer, the first conductive line is arranged in the groove, and a surface of the first conductive line away from the base substrate is flush with a surface of the buffer layer away from the base substrate.
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公开(公告)号：US20210159279A1
公开(公告)日：2021-05-27
申请号：US17043962
申请日：2020-04-22
Inventor： Jun LIU , Liangchen YAN , Bin ZHOU , Wei LI , Tongshang SU , Yongchao HUANG , Biao LUO , Xuehai GUI
IPC: H01L27/32
Abstract: An array substrate is provided, including a base substrate, a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode that are sequentially provided, and further including a first insulating layer, a second insulating layer, a third insulating layer, at least one first via, and at least one second via. Each first via penetrates through the third insulating layer, and in each pixel unit with plural chromatic color resists, each first via is between adjacent two chromatic color resists and filled by one of the adjacent two chromatic color resists. Each second via penetrates through the second insulating layer, the at least one second via is in one-to-one correspondence with the at least one first via, each second via is filled by a chromatic color resist having a same color as that of the chromatic color resist in the corresponding first via.
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公开(公告)号：US20200273995A1
公开(公告)日：2020-08-27
申请号：US16706160
申请日：2019-12-06
Inventor： Wei SONG , Ce ZHAO , Yuankui DING , Ming WANG , Jun LIU , Yingbin HU , Wei LI , Liusong NI
IPC: H01L29/786 , H01L27/12
Abstract: The present disclosure provides a transistor and a manufacturing method thereof, a display substrate and a display device. The transistor includes: a base structure; an active layer on the base structure; and a gate electrode, a source electrode and a drain electrode that are all located on a side of the active layer distal to the base structure. The active layer includes a first region corresponding to an orthographic projection of the gate electrode on the base structure and a second region outside the orthographic projection. A surface of the base structure in contact with the active layer in the first region is not in the same plane as a surface of the base structure in contact with the active layer in the second region. The active layer in the first region has substantially the same thickness as a thickness of the active layer in the second region.
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公开(公告)号：US20200168687A1
公开(公告)日：2020-05-28
申请号：US16441422
申请日：2019-06-14
Inventor： Yingbin HU , Liangchen YAN , Ce ZHAO , Yuankui DING , Yang ZHANG , Yongchao HUANG , Luke DING , Jun LIU
Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.
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公开(公告)号：US20200075704A1
公开(公告)日：2020-03-05
申请号：US16456619
申请日：2019-06-28
Inventor： Jun LIU , Liangchen YAN , Bin ZHOU , Jun WANG , Tongshang SU , Biao LUO , Yang ZHANG
Abstract: An array substrate includes a base substrate, a transistor on the base substrate, a planarization layer on a side of the transistor away from the base substrate, a recessed portion on the planarization layer, and a light blocking portion in the recessed portion. The light blocking portion is configured to prevent a light from being incident upon an active layer.
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