公开(公告)号：US11567870B2

公开(公告)日：2023-01-31

申请号：US17215435

申请日：2021-03-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Jamshed Jalal ,  Tushar P. Ringe ,  Jesse Garrett Beu

IPC: G06F12/08 ,  G06F12/0831 ,  G06F12/0891 ,  G06F12/084

Abstract: An apparatus comprises snoop filter storage circuitry to store snoop filter entries corresponding to addresses and comprising sharer information. Control circuitry selects which sharers, among a plurality of sharers capable of holding cached data, should be issued with snoop requests corresponding to a target address, based on the sharer information of the snoop filter entry corresponding to the target address. The control circuitry is capable of setting a given snoop filter entry corresponding to a given address to an imprecise encoding in which the sharer information provides an imprecise description of which sharers hold cached data corresponding to the given address, and the given snoop filter entry comprises at least one sharer count value indicative of a number of sharers holding cached data corresponding to the given address.

公开(公告)号：US20210097173A1

公开(公告)日：2021-04-01

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  H03K19/003 ,  G11C13/00

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US20210064371A1

公开(公告)日：2021-03-04

申请号：US16550644

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Alejandro Rico Carro ,  Joshua Randall ,  Jose Alberto Joao

IPC: G06F9/30 ,  G06F9/52 ,  G06F9/48 ,  G06F9/50 ,  G06F12/0842

Abstract: A method and apparatus for application thread prioritization to mitigate the effects of operating system noise is disclosed. The method generally includes executing in parallel a plurality of application threads of a parallel application. An interrupt condition of an application thread of the plurality of application threads is detected. A priority of the interrupted application thread is changed relative to priorities of one or more other application threads of the plurality of application threads, and control is returned to the interrupted application thread after the interrupt condition. The interrupted application thread then resumes execution in accordance with the changed priority.

公开(公告)号：US11841943B2

公开(公告)日：2023-12-12

申请号：US16584865

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Joshua Randall ,  Joel Thornton Irby ,  Carl Wayne Vineyard ,  Mudit Bhargava

IPC: G06F21/55 ,  G11C13/00 ,  H03K19/003

CPC classification number: G06F21/554 ,  G11C13/004 ,  G11C13/0069 ,  H03K19/003 ,  G06F2221/034

Abstract: Various implementations described herein refer to a method for tracking abnormal incidents while monitoring activity of logic circuitry. The method may include detecting a tamper event related to the abnormal incidents and storing an attack signature related to the tamper event. The attack signature may be stored in non-volatile memory (NVM), such as, e.g., correlated electron random access memory (CeRAM).

公开(公告)号：US20230029860A1

公开(公告)日：2023-02-02

申请号：US17388927

申请日：2021-07-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Alejandro Rico Carro ,  Dam Sunwoo ,  Saurabh Pijuskumar Sinha ,  Jamshed Jalal

IPC: G06F12/0811 ,  G06F12/084 ,  G06F12/0813 ,  H04L12/933 ,  H04L12/717

Abstract: Various implementations described herein are directed to a device with a multi-layered logic structure with multiple layers including a first layer and a second layer arranged vertically in a stacked configuration. The device may have a first cache memory with first interconnect logic disposed in the first layer. The device may have a second cache memory with second interconnect logic disposed in the second layer, wherein the second interconnect logic in the second layer is linked to the first interconnect logic in the first layer.

公开(公告)号：US20220308999A1

公开(公告)日：2022-09-29

申请号：US17215435

申请日：2021-03-29

Applicant: Arm Limited

Inventor： Joshua Randall ,  Jamshed Jalal ,  Tusher P. Ringe ,  Jesse Garrett Beu

IPC: G06F12/0831 ,  G06F12/084 ,  G06F12/0891

Abstract: An apparatus comprises snoop filter storage circuitry to store snoop filter entries corresponding to addresses and comprising sharer information. Control circuitry selects which sharers, among a plurality of sharers capable of holding cached data, should be issued with snoop requests corresponding to a target address, based on the sharer information of the snoop filter entry corresponding to the target address. The control circuitry is capable of setting a given snoop filter entry corresponding to a given address to an imprecise encoding in which the sharer information provides an imprecise description of which sharers hold cached data corresponding to the given address, and the given snoop filter entry comprises at least one sharer count value indicative of a number of sharers holding cached data corresponding to said address.

公开(公告)号：US11263137B2

公开(公告)日：2022-03-01

申请号：US16884359

申请日：2020-05-27

Applicant: Arm Limited

Inventor： Jose Alberto Joao ,  Tiago Rogerio Muck ,  Joshua Randall ,  Alejandro Rico Carro ,  Bruce James Mathewson

IPC: G06F12/00 ,  G06F12/0842 ,  G06F12/0875

Abstract: A method and apparatus is disclosed for transferring data from a first processor core to a second processor core. The first processor core executes a stash instruction having a first operand associated with a data address of the data. A second processor core is determined to be a stash target for a stash message, based on the data address or a second operand. A stash message is sent to the second processor core, notifying the second processor core of the written data. Responsive to receiving the stash message, the second processor core can opt to store the data in its cache. The data may be included in the stash message or retrieved in response to a read request by the second processing core. The second processor core may be determined by prediction based, at least in part, on monitored data transactions.