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    Systems and methods for detecting replay attacks on security space
    13.
    发明授权
    Systems and methods for detecting replay attacks on security space 有权

    公开(公告)号：US11374967B2

    公开(公告)日：2022-06-28

    申请号：US16276504

    申请日：2019-02-14

    Applicant: Apple Inc.

    Inventor： Zhimin Chen ,  Timothy R. Paaske ,  Gilbert H. Herbeck

    IPC: G06F21/64 ,  H04L9/40 ,  G06F21/57 ,  G06F21/71 ,  G06F21/74 ,  G06F12/14

    Abstract: A system and method for detecting replay attacks on secure data are disclosed. A system on a chip (SOC) includes a security processor. Blocks of data corresponding to sensitive information are stored in off-chip memory. The security processor uses an integrity data structure, such as an integrity tree, for the blocks. The intermediate nodes of the integrity tree use nonces which have been generated independent of any value within a corresponding block. By using only the nonces to generate tags in the root at the top layer stored in on-chip memory and the nodes of the intermediate layers stored in off-chip memory, an amount of storage used is reduced for supporting the integrity tree. When the security processor detects events which create access requests for one or more blocks, the security processor uses the integrity tree to verify a replay attack has not occurred and corrupted data.

    Authentication and control of encryption keys
    14.
    发明授权
    Authentication and control of encryption keys 有权

    公开(公告)号：US11263306B2

    公开(公告)日：2022-03-01

    申请号：US16927934

    申请日：2020-07-13

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Weihua Mao ,  Shu-Yi Yu

    IPC: G06F21/00 ,  G06F21/46 ,  G06F21/60 ,  G06F21/44 ,  G06F21/85 ,  H04L9/08

    Abstract: An apparatus, a method, and a system are presented in which the apparatus includes an interface control circuit that may be configured to receive a message including a cryptographic keyword and a policy value. The policy value may include one or more data bits indicative of one or more policies that define allowable usage of the cryptographic keyword. The apparatus also includes a security circuit that may be configured to extract the cryptographic keyword and the policy value from the message, and to apply at least one policy of the one or more policies to usage of the cryptographic keyword in response to a determination that an authentication of the message succeeded.

    MARKING VALID RETURN TARGETS
    17.
    发明申请
    MARKING VALID RETURN TARGETS 审中-公开
    标记有效的返回目标

    公开(公告)号：US20170024559A1

    公开(公告)日：2017-01-26

    申请号：US14807609

    申请日：2015-07-23

    Applicant: Apple Inc.

    Inventor： Gregory D. Hughes ,  Conrado Blasco ,  Gerard R. Williams, III ,  Jacques Anthony Vidrine ,  Jeffry E. Gonion ,  Timothy R. Paaske ,  Tristan F. Schaap

    IPC: G06F21/54

    CPC classification number: G06F21/54

    Abstract: Systems, apparatuses, methods, and computer-readable mediums for preventing return oriented programming (ROP) attacks. A compiler may insert landing pads adjacent to valid return targets in an instruction sequence. When a return instruction is executed, the processor may treat the return as suspicious if the target of the return instruction does not have an adjacent landing pad. Additionally, each landing pad may be encoded with a color, and a colored launch pad may be inserted into the instruction stream next to each return instruction. When a return instruction is executed, the processor may determine if the target of the return has a landing pad with the same color as the launch pad of the return instruction. Return-target pairs with color mismatches may be treated as suspicious and the offending process may be killed.

    Abstract translation: 用于防止返回定向编程（ROP）攻击的系统，装置，方法和计算机可读介质。 编译器可以在指令序列中插入与有效返回目标相邻的着陆焊盘。 当执行返回指令时，如果返回指令的目标没有相邻的着陆垫，则处理器可以将返回值视为可疑。 此外，每个着陆垫可以用颜色编码，并且彩色的发射板可以插入每个返回指令旁边的指令流中。 当执行返回指令时，处理器可以确定返回目标是否具有与返回指令的发射台相同颜色的着陆键盘。 具有颜色不匹配的返回目标对可能被视为可疑的，并且违规进程可能被杀死。

    AUTHENTICATION AND CONTROL OF ENCRYPTION KEYS
    18.
    发明申请
    AUTHENTICATION AND CONTROL OF ENCRYPTION KEYS 有权
    加密钥的验证与控制

    公开(公告)号：US20160314295A1

    公开(公告)日：2016-10-27

    申请号：US14696581

    申请日：2015-04-27

    Applicant: Apple Inc.

    Inventor： Timothy R. Paaske ,  Weihua Mao ,  Shu-Yi Yu

    IPC: G06F21/46 ,  G06F21/60

    CPC classification number: G06F21/46 ,  G06F21/44 ,  G06F21/602 ,  G06F21/606 ,  G06F21/85 ,  G06F2221/2137 ,  H04L9/088

    Abstract: An apparatus, a method, and a system are presented in which the apparatus may include a security circuit, a processor, and an interface controller. The security circuit may be configured to generate a keyword. The processor may be configured to determine one or more policies to be applied to usage of the keyword, and to generate a policy value. The policy value may include one or more data bits indicative of the determined one or more policies. The interface controller may be configured to generate a message including the keyword and the policy value. The interface controller may also be configured to send the message.

    Abstract translation: 提供了一种装置，方法和系统，其中装置可以包括安全电路，处理器和接口控制器。 安全电路可以被配置为生成关键字。 处理器可以被配置为确定要应用于关键字的使用的一个或多个策略，并且生成策略值。 策略值可以包括指示所确定的一个或多个策略的一个或多个数据比特。 接口控制器可以被配置为生成包括关键字和策略值的消息。 接口控制器还可以被配置为发送消息。

    Reducing latency in a peripheral component interconnect express link
    20.
    发明授权
    Reducing latency in a peripheral component interconnect express link 有权
    减少外设组件互连中的延迟快速链接

    公开(公告)号：US09015396B2

    公开(公告)日：2015-04-21

    申请号：US13622266

    申请日：2012-09-18

    Applicant: Apple Inc.

    Inventor： Michael W. Murphy ,  Joshua P. de Cesare ,  Timothy R. Paaske

    IPC: G06F13/24 ,  G06F1/32 ,  G06F1/00

    CPC classification number: G06F13/24 ,  G06F1/3253 ,  Y02D10/151

    Abstract: A method and system are described for reducing latency in a peripheral component interconnect express (PCIe) link between a host and an endpoint. In the described embodiments, an interrupt is issued from the endpoint to the host using the PCIe link. Then, while the interrupt is pending at the host, the PCIe link is prevented from entering a power-saving mode with an exit latency greater than a predetermined time period.

    Abstract translation: 描述了一种用于减少主机和端点之间的外围组件互连快速（PCIe）链路中的延迟的方法和系统。 在所描述的实施例中，使用PCIe链路从端点向主机发出中断。 然后，当中断在主机处于等待状态时，PCIe链路被阻止进入功率节省模式，退出延迟大于预定时间段。

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