公开(公告)号：US11658671B2

公开(公告)日：2023-05-23

申请号：US17482322

申请日：2021-09-22

Applicant: Apple Inc.

Inventor： Ryan D. Bartling ,  Jafar Savoj ,  Brian S. Leibowitz ,  Shah M. Sharif

IPC: H03M1/00 ,  H03M1/06

CPC classification number: H03M1/0687 ,  H03M1/0626 ,  H03M1/0648 ,  H03M1/0663

Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.

公开(公告)号：US11502880B1

公开(公告)日：2022-11-15

申请号：US17478069

申请日：2021-09-17

Applicant: Apple Inc.

Inventor： Ryan D. Bartling ,  Jafar Savoj ,  Brian S. Leibowitz

IPC: H04L25/03 ,  H04L25/06 ,  H04L7/00

Abstract: A receiver converter circuit included in a computer system may receive multiple signals that encode a serial data stream that encode multiple data symbols. To correct for baseline wander, the receiver circuit may generate a disparity signal that is used to control the application of a differential voltage to the multiple signals. The receiver circuit may also employ the disparity signal to generate a gradient against which the magnitude of differential voltage is calibrated.