公开(公告)号：US20150039867A1

公开(公告)日：2015-02-05

申请号：US13956291

申请日：2013-07-31

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/34 ,  G06F9/384 ,  G06F9/3857

Abstract: Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In this embodiment, the instruction includes one or more location values that are each usable to identify an operand for the instruction. In this embodiment, a method may include accessing operands using the location values and assigning accessed operands to sources using the mapping values. In one embodiment, the sources may correspond to inputs of an execution block. In one embodiment, a destination mapping value in the instruction may specify a location value that indicates a destination for storing an instruction result.

Abstract translation: 公开了关于指令操作数的指定的技术。 在一些实施例中，这可以涉及将操作数分配给源输入。 在一个实施例中，指令包括一个或多个映射值，每个映射值对应于指令的源，并且每个映射值指定位置值。 在本实施例中，指令包括一个或多个位置值，每个位置值可用于识别指令的操作数。 在该实施例中，方法可以包括使用位置值访问操作数，并使用映射值将访问的操作数分配给源。 在一个实施例中，源可以对应于执行块的输入。 在一个实施例中，指令中的目标映射值可以指定指示用于存储指令结果的目的地的位置值。

公开(公告)号：US20150039661A1

公开(公告)日：2015-02-05

申请号：US13954936

申请日：2013-07-30

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: H03M7/24

CPC classification number: H03M7/24 ,  G06F9/30025

Abstract: Techniques are disclosed relating to type conversion using a floating-point unit. In one embodiment, to convert a floating-point value to a normalized integer format, a floating-point unit is configured to perform an operation to generate a result having a significant portion and an exponent portion, where the operation includes multiplying the floating-point value by a constant. In one embodiment, the apparatus is further configured to add a value to the exponent portion of the result, and set a rounding mode to round to nearest. The constant may be a greatest value less than one that can be represented using the particular number of unsigned bits. The value added to the initial exponent may be equal to the number of unsigned bits of the normalized integer format. The apparatus may perform this conversion in response to a pack instruction.

Abstract translation: 公开了关于使用浮点单元的类型转换的技术。 在一个实施例中，为了将浮点值转换为归一化的整数格式，浮点单元被配置为执行用于产生具有有效部分和指数部分的结果的操作，其中操作包括将浮点 值由常数。 在一个实施例中，该装置还被配置为向结果的指数部分添加值，并将舍入模式设置为舍入至最接近。 常数可以是小于可以使用特定数目的无符号位来表示的最大值。 添加到初始指数的值可以等于归一化整数格式的无符号位数。 该装置可以响应于包指令执行该转换。

公开(公告)号：US09652233B2

公开(公告)日：2017-05-16

申请号：US13971782

申请日：2013-08-20

Applicant: Apple Inc.

Inventor： Terence M. Potter ,  Timothy A. Olson ,  James S. Blomgren ,  Andrew M. Havlir ,  Michael Geary

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06T1/60 ,  G06F12/0875 ,  G06F12/0862

CPC classification number: G06F9/30043 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06T1/60 ,  Y02D10/13

Abstract: Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may be used to store a subset of operands, and may use less power and have quicker access times than the register file. Hint values may be used in some embodiments to suggest that a particular operand should be stored in the operand cache (so that is available for current or future use). In one embodiment, a hint value indicates that an operand should be cached whenever possible. Hint values may be determined by software, such as a compiler, in some embodiments. One or more criteria may be used to determine hint values, such as how soon in the future or how frequently an operand will be used again.

公开(公告)号：US09508112B2

公开(公告)日：2016-11-29

申请号：US13956299

申请日：2013-07-31

Applicant: Apple Inc.

Inventor： Andrew M. Havlir ,  James S. Blomgren ,  Terence M. Potter

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06T1/20 ,  G06F9/3012 ,  G06F9/30138 ,  G06F9/3826 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3873 ,  G06T1/60

Abstract: Techniques are disclosed relating to a multithreaded execution pipeline. In some embodiments, an apparatus is configured to assign a number of threads to an execution pipeline that is an integer multiple of a minimum number of cycles that an execution unit is configured to use to generate an execution result from a given set of input operands. In one embodiment, the apparatus is configured to require strict ordering of the threads. In one embodiment, the apparatus is configured so that the same thread access (e.g., reads and writes) a register file in a given cycle. In one embodiment, the apparatus is configured so that the same thread does not write back an operand and a result to an operand cache in a given cycle.

Abstract translation: 公开了涉及多线程执行流水线的技术。 在一些实施例中，设备被配置为向执行流水线分配多个线程，该执行流水线是执行单元被配置为用于从给定的一组输入操作数生成执行结果的最小循环数的整数倍。 在一个实施例中，该装置被配置为要求严格排列螺纹。 在一个实施例中，设备被配置为使得在给定周期中相同的线程访问（例如，读取和写入）寄存器文件。 在一个实施例中，该设备被配置为使得相同的线程不在给定周期中将操作数和结果写回操作数高速缓存。

公开(公告)号：US09292285B2

公开(公告)日：2016-03-22

申请号：US13970563

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： James S. Blomgren

IPC: G06F7/483 ,  G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014

Abstract: Techniques are disclosed relating to floating-point operations in computer processors. In one embodiment, an apparatus includes a floating-point unit and circuitry configured to receive an initial value X for a floating-point operation. In this embodiment, X is between 0 and 1.0 inclusive. In this embodiment, the circuitry is configured to generate first and second floating-point values based on an exponent of X that sum to 1. In this embodiment, the floating-point unit is configured to perform an operation using the first and second floating-point values. The apparatus may reduce drift, in this embodiment, when a floating-point representation of X does not guarantee that the sum of X and (1−X) is 1. The apparatus may be configured to perform blending and/or interpolation operations using the first and second floating-point values.

Abstract translation: 公开了关于计算机处理器中的浮点运算的技术。 在一个实施例中，一种装置包括浮点单元和经配置以接收用于浮点运算的初始值X的电路。 在该实施例中，X在0和1.0之间，包括0和1.0。 在本实施例中，电路被配置为基于X的指数生成第一和第二浮点值，其总和为1.在本实施例中，浮点单元被配置为使用第一和第二浮点数执行操作， 点值。 在本实施例中，当X的浮点表示不能保证X和（1-X）的和为1时，该装置可以减少漂移。该装置可以被配置为执行混合和/或插值操作，使用 第一和第二个浮点值。

公开(公告)号：US09264066B2

公开(公告)日：2016-02-16

申请号：US13954936

申请日：2013-07-30

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: G06F9/30 ,  H03M7/24

CPC classification number: H03M7/24 ,  G06F9/30025

Abstract: Techniques are disclosed relating to type conversion using a floating-point unit. In one embodiment, to convert a floating-point value to a normalized integer format, a floating-point unit is configured to perform an operation to generate a result having a significant portion and an exponent portion, where the operation includes multiplying the floating-point value by a constant. In one embodiment, the apparatus is further configured to add a value to the exponent portion of the result, and set a rounding mode to round to nearest. The constant may be a greatest value less than one that can be represented using the particular number of unsigned bits. The value added to the initial exponent may be equal to the number of unsigned bits of the normalized integer format. The apparatus may perform this conversion in response to a pack instruction.

Abstract translation: 公开了关于使用浮点单元的类型转换的技术。 在一个实施例中，为了将浮点值转换为归一化的整数格式，浮点单元被配置为执行用于产生具有有效部分和指数部分的结果的操作，其中操作包括将浮点 值由常数。 在一个实施例中，该装置还被配置为向结果的指数部分添加值，并将舍入模式设置为舍入至最接近。 常数可以是小于可以使用特定数目的无符号位来表示的最大值。 添加到初始指数的值可以等于归一化整数格式的无符号位数。 该装置可以响应于包指令执行该转换。

公开(公告)号：US20150058573A1

公开(公告)日：2015-02-26

申请号：US13971811

申请日：2013-08-20

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter ,  Timothy A. Olson ,  Andrew M. Havlir

IPC: G06F12/08 ,  G06F9/30

CPC classification number: G06F12/0875 ,  G06F9/30043 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30185

Abstract: Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may be used to store a subset of operands, and may use less power and have quicker access times than the register file. Selectors (e.g., multiplexers) may be used to read operands from the operand cache. Power savings may be achieved in some embodiments by activating only a subset of the selectors, which may be done by activators (e.g. flip-flops). Operands may also be concurrently provided to two or more locations via forwarding, which may be accomplished via a source selection unit in some embodiments. Operand forwarding may also reduce power and/or speed execution in one or more embodiments.

Abstract translation: 指令可能需要执行一个或多个操作数，可以从寄存器文件提供。 然而，在GPU的上下文中，寄存器文件可以是相对较大的结构，并且从寄存器文件的读取可能是能量和/或时间密集的。操作数高速缓存可以用于存储操作数的子集，并且可以使用较少的 并且具有比寄存器文件更快的访问时间。 选择器（例如，多路复用器）可用于从操作数高速缓存读取操作数。 在一些实施例中可以通过激活选择器的子集来实现功率节省，这可以由激活器（例如，触发器）完成。 操作数还可以经由转发同时提供给两个或更多个位置，这在一些实施例中可以经由源选择单元来实现。 操作数转发还可以在一个或多个实施例中降低功率和/或速度执行。

公开(公告)号：US20150052335A1

公开(公告)日：2015-02-19

申请号：US13970563

申请日：2013-08-19

Applicant: Apple Inc.

Inventor： James S. Blomgren

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014

Abstract: Techniques are disclosed relating to floating-point operations in computer processors. In one embodiment, an apparatus includes a floating-point unit and circuitry configured to receive an initial value X for a floating-point operation. In this embodiment, X is between 0 and 1.0 inclusive. In this embodiment, the circuitry is configured to generate first and second floating-point values based on an exponent of X that sum to 1. In this embodiment, the floating-point unit is configured to perform an operation using the first and second floating-point values. The apparatus may reduce drift, in this embodiment, when a floating-point representation of X does not guarantee that the sum of X and (1−X) is 1. The apparatus may be configured to perform blending and/or interpolation operations using the first and second floating-point values.

Abstract translation: 公开了关于计算机处理器中的浮点运算的技术。 在一个实施例中，一种装置包括浮点单元和经配置以接收用于浮点运算的初始值X的电路。 在该实施例中，X在0和1.0之间，包括0和1.0。 在本实施例中，电路被配置为基于X的指数生成第一和第二浮点值，其总和为1.在本实施例中，浮点单元被配置为使用第一和第二浮点数执行操作， 点值。 在本实施例中，当X的浮点表示不能保证X和（1-X）的和为1时，该装置可以减少漂移。该装置可以被配置为执行混合和/或插值操作，使用 第一和第二个浮点值。

公开(公告)号：US09632785B2

公开(公告)日：2017-04-25

申请号：US15233496

申请日：2016-08-10

Applicant: Apple Inc.

Inventor： James S. Blomgren ,  Terence M. Potter

IPC: G06F9/00 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/30007 ,  G06F9/34 ,  G06F9/384 ,  G06F9/3857

Abstract: Techniques are disclosed relating to specification of instruction operands. In some embodiments, this may involve assigning operands to source inputs. In one embodiment, an instruction includes one or more mapping values, each of which corresponds to a source of the instruction and each of which specifies a location value. In this embodiment, the instruction includes one or more location values that are each usable to identify an operand for the instruction. In this embodiment, a method may include accessing operands using the location values and assigning accessed operands to sources using the mapping values. In one embodiment, the sources may correspond to inputs of an execution block. In one embodiment, a destination mapping value in the instruction may specify a location value that indicates a destination for storing an instruction result.

公开(公告)号：US09459869B2

公开(公告)日：2016-10-04

申请号：US13971800

申请日：2013-08-20

Applicant: Apple Inc.

Inventor： Timothy A. Olson ,  Terence M. Potter ,  James S. Blomgren ,  Andrew M. Havlir

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F9/30 ,  G06F9/38 ,  G06T1/20 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06T1/20 ,  Y02D10/13

Abstract: Instructions may require one or more operands to be executed, which may be provided from a register file. In the context of a GPU, however, a register file may be a relatively large structure, and reading from the register file may be energy and/or time intensive An operand cache may store a subset of operands, and may use less power and have quicker access times than the register file. In some embodiments, intelligent operand prefetching may speed execution by reducing memory bank conflicts (e.g., conflicts within a register file containing multiple memory banks). An unused operand slot for another instruction (e.g., an instruction that does not require a maximum number of source operands allowed by an instruction set architecture) may be used to prefetch an operand for another instruction in one embodiment. Prefetched operands may be stored in an operand cache, and prefetching may occur based on software-provided information.

Abstract translation: 指令可能需要执行一个或多个操作数，这可以从寄存器文件提供。 然而，在GPU的上下文中，寄存器文件可以是相对较大的结构，并且从寄存器文件的读取可能是能量和/或时间密集的。操作数高速缓存可以存储操作数的子集，并且可以使用更少的功率并具有 比寄存器文件更快的访问时间。 在一些实施例中，智能操作数预取可以通过减少存储体冲突（例如，包含多个存储体的寄存器文件内的冲突）来加速执行。 在一个实施例中，用于另一指令的未用操作数时隙（例如，不需要由指令集体系结构允许的最大数量的源操作数的指令）可用于预取另一指令的操作数。 预取操作数可以存储在操作数缓存中，并且可以基于软件提供的信息进行预取。