公开(公告)号：US12182427B2

公开(公告)日：2024-12-31

申请号：US17966071

申请日：2022-10-14

Applicant: Arm Limited

Inventor： Stefano Ghiggini ,  Natalya Bondarenko ,  Luca Nassi ,  Geoffray Matthieu Lacourba ,  Huzefa Moiz Sanjeliwala ,  Miles Robert Dooley ,  Abhishek Raja

IPC: G06F3/06

Abstract: An apparatus is provided for controlling the operating mode of control circuitry, such that the control circuitry may change between two operating modes. In an allocation mode, data that is loaded in response to an instruction is allocated into storage circuitry from an intermediate buffer, and the data is read from the storage circuitry. In a non-allocation mode, the data is not allocated to the storage circuitry, and is read directly from intermediate buffer. The control of the operating mode may be performed by mode control circuitry, and the mode may be changed in dependence on the type of instruction that calls the data, and whether the data may be used again in the near future, or whether it is expected to be used only once.

公开(公告)号：US12045618B2

公开(公告)日：2024-07-23

申请号：US17209515

申请日：2021-03-23

Applicant: Arm Limited

Inventor： Natalya Bondarenko ,  Stefano Ghiggini ,  Geoffray Matthieu Lacourba ,  Cédric Denis Robert Airaud

IPC: G06F9/38 ,  G06N20/00

CPC classification number: G06F9/3802 ,  G06F9/383 ,  G06N20/00

Abstract: The invention provides a data processing apparatus and a data processing method for generating prefetches of data for use during execution of instructions by processing circuitry. The prefetches that are generated are based on a nested prefetch pattern. The nested prefetch pattern comprises a first pattern and a second pattern. The first pattern is defined by a first address offset between sequentially accessed addresses and a first observed number of the sequentially accessed addresses separated by the first address offset. The second pattern is defined by a second address offset between sequential iterations of the first pattern and a second observed number of the sequential iterations of the first pattern separated by the second address offset.

公开(公告)号：US11016902B2

公开(公告)日：2021-05-25

申请号：US16382394

申请日：2019-04-12

Applicant: Arm Limited

Inventor： Geoffray Matthieu Lacourba ,  Andrew John Turner ,  Alex James Waugh

IPC: G06F12/0868 ,  G06F13/14 ,  G06F13/38

Abstract: Circuitry comprises a data store to hold status data indicating a status of a first set of one or more devices connected to the interconnect circuitry; and control circuitry, responsive to initiation of a data handling transaction, to generate recovery data indicative of an initial state of the status data and to predict a predicted revised state of the status data applicable to resolution of the data handling transaction; the control circuitry being configured to change the status data to the predicted revised state in response to initiation of the transaction and before resolution of the transaction, and in response to a request to access the status data between the change of the status data to the predicted revised state and the resolution of the transaction, to provide access to the initial state of the status data, using the recovery data.

公开(公告)号：US09122613B2

公开(公告)日：2015-09-01

申请号：US13788538

申请日：2013-03-07

Applicant: ARM Limited

Inventor： Geoffray Matthieu Lacourba ,  Philippe Jean-Pierre Raphalen

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F9/383 ,  G06F9/3832 ,  G06F12/0811 ,  G06F2212/6024 ,  G06F2212/6026 ,  Y02D10/13

Abstract: A data processing apparatus includes a processor and a hierarchical data storage system, including a memory and a cache, for storing the data and the instructions in storage locations identified by physical addresses. The apparatus includes address translation circuitry for mapping the virtual addresses to the physical addresses and load store circuitry receiving access requests from the processor. The store circuitry accesses the translation circuitry to identify physical addresses that correspond to virtual addresses of the received data access requests, and to access the corresponding physical addresses in the hierarchical data storage system. Preload circuitry receives preload requests from the processor indicating virtual addresses storage locations that are to be preloaded. Prefetch circuitry monitors at least some of the accesses performed by the load store circuitry and predicts addresses to be accessed subsequently, and transmits the predicted addresses to the preload circuitry as preload requests.

Abstract translation: 数据处理装置包括处理器和分层数据存储系统，包括存储器和高速缓存，用于将数据和指令存储在由物理地址识别的存储位置中。 该设备包括用于将虚拟地址映射到物理地址的地址转换电路，以及从处理器接收访问请求的加载存储电路。 存储电路访问转换电路以识别对应于接收到的数据访问请求的虚拟地址的物理地址，并访问分层数据存储系统中的相应物理地址。 预加载电路从处理器接收指示要预加载的虚拟地址存储位置的预加载请求。 预取电路监视由加载存储电路执行的至少一些访问，并预测随后要访问的地址，并将预测地址作为预加载请求发送到预加载电路。