公开(公告)号：US20230359259A1

公开(公告)日：2023-11-09

申请号：US18351248

申请日：2023-07-12

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3206 ,  G06F1/324 ,  G06F1/3296 ,  G06F1/3287 ,  G06F1/3209

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/00

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances.

公开(公告)号：US09824171B2

公开(公告)日：2017-11-21

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

公开(公告)号：US20170039299A1

公开(公告)日：2017-02-09

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract translation: 在一些实施例中，寄存器文件电路设计过程包括指示自动集成电路设计程序产生寄存器文件电路设计，包括提供单元电路设计并指示自动化集成电路设计程序产生选择设计，预解码 设计和数据门控设计。 单元电路设计描述了具有特定布置的多个选择电路。 选择设计描述了包括具有特定布置的相应多个选择电路的多个复制电路。 预解码设计描述了预解码电路，其被配置为识别由写指令的一部分识别的多个条目。 数据门控设计描述了数据选通电路，其响应于未识别相应条目的预解码电路而配置，以禁止连接到各个条目的相应写入选择电路的数据输入。

公开(公告)号：US09454196B2

公开(公告)日：2016-09-27

申请号：US13929331

申请日：2013-06-27

Applicant: Apple Inc.

Inventor： Matthias Knoth ,  Rohit Kumar ,  Eric Smith ,  Louis Luh

IPC: H02J7/00 ,  G06F1/26 ,  H02J1/10 ,  H02J7/34 ,  H02J1/02

CPC classification number: G06F1/26 ,  H02J1/02 ,  H02J1/10 ,  H02J7/345 ,  Y10T307/527

Abstract: In some embodiments, a system may include at least one voltage controller. At least one of the voltage controllers may assess, during use, an occurrence of a predetermined condition. In some embodiments, the system may include an at least first capacitor. The at least first capacitor may be coupled to at least one of the voltage controllers such that at least one of the voltage controllers engages the at least first capacitor to supply additional current when the predetermined condition occurs. When the increase in current is no longer required the at least first capacitor may be disengaged. The at least first capacitor may be charged when disengaged until a predetermined capacity.

Abstract translation: 在一些实施例中，系统可以包括至少一个电压控制器。 至少一个电压控制器可以在使用期间评估预定条件的发生。 在一些实施例中，系统可以包括至少第一电容器。 至少第一电容器可以耦合到至少一个电压控制器，使得当预定条件发生时，至少一个电压控制器接合至少第一电容器以提供附加电流。 当电流的增加不再需要时，可以使至少第一电容器分离。 至少第一电容器可以在分离直到预定容量时被充电。

公开(公告)号：US20230122955A1

公开(公告)日：2023-04-20

申请号：US17821394

申请日：2022-08-22

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3209 ,  G06F1/3296 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287

Abstract: An integrated circuit may include multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g., to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US20190050043A1

公开(公告)日：2019-02-14

申请号：US16159821

申请日：2018-10-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US10101788B2

公开(公告)日：2018-10-16

申请号：US15433201

申请日：2017-02-15

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

公开(公告)号：US09383806B2

公开(公告)日：2016-07-05

申请号：US13864723

申请日：2013-04-17

Applicant: Apple Inc.

Inventor： Wei-Han Lien ,  Gerard R Williams, III ,  Rohit Kumar ,  Sandeep Gupta ,  Suresh Periyacheri ,  Shih-Chieh R Wen

IPC: G06F1/32

CPC classification number: G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/172

Abstract: An apparatus for performing instruction throttling for a multi-processor system is disclosed. The apparatus may include a power estimation circuit, a table, a comparator, and a finite state machine. The power estimation circuit may be configured to receive information on high power instructions issued to a first processor and a second processor, and generate a power estimate dependent upon the received information. The table may be configured to store one or more pre-determined power threshold values, and the comparator may be configured to compare the power estimate with at least one of the pre-determined power threshold values. The finite state machine may be configured to adjust the throttle level of the first and second processors dependent upon the result of the comparison.

Abstract translation: 公开了一种用于执行多处理器系统的指令调节的装置。 该装置可以包括功率估计电路，表，比较器和有限状态机。 功率估计电路可以被配置为接收关于发给第一处理器和第二处理器的高功率指令的信息，并且根据所接收的信息生成功率估计。 该表可以被配置为存储一个或多个预定功率阈值，并且比较器可以被配置为将功率估计与预定功率阈值中的至少一个进行比较。 有限状态机可以被配置为根据比较的结果来调节第一和第二处理器的节气门位置。

公开(公告)号：US20150253836A1

公开(公告)日：2015-09-10

申请号：US14200216

申请日：2014-03-07

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/32

CPC classification number: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/171 ,  Y02D10/172

Abstract: In an embodiment, an integrated circuit includes multiple instances of a component (e.g. a processor) and a control circuit. The instances may be configured to operate in various modes. Some of the modes are incapable of presenting a worst-case load on the power supply. The control circuit may be configured to monitor the instances and detect the modes in which the instances are operating. Based on the monitoring, the control circuit may request to recover a portion of the voltage margin established for worst-case conditions in the instances. If the instances are to change modes, they may be configured to request mode change from the control circuit. If the mode change causes an increase in the current supply voltage magnitude (e.g. to restore some of the recovered voltage margin), the control circuit may cause the restore and permit it to complete prior to granting the mode change.

Abstract translation: 在一个实施例中，集成电路包括组件（例如处理器）和控制电路的多个实例。 这些实例可以被配置为以各种模式操作。 一些模式不能在电源上呈现最坏的负载。 控制电路可以被配置为监视实例并检测实例正在操作的模式。 基于监视，控制电路可以请求恢复在实例中为最坏情况条件建立的电压余量的一部分。 如果实例要改变模式，则它们可以被配置为从控制电路请求模式改变。 如果模式改变导致当前电源电压幅度的增加（例如，恢复一些恢复的电压余量），则控制电路可以在授予模式改变之前导致恢复并允许其恢复。

公开(公告)号：US20250093936A1

公开(公告)日：2025-03-20

申请号：US18970560

申请日：2024-12-05

Applicant: Apple Inc.

Inventor： John H. Mylius ,  Conrad H. Ziesler ,  Daniel C. Murray ,  Jong-Suk Lee ,  Rohit Kumar

IPC: G06F1/3209 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296

Abstract: A system include multiple components configured to operate in different modes with different power supply loads. Control circuitry may determine a first voltage margin to be included in a power supply voltage magnitude requested for the components based on current operating modes of the multiple components and detect that a first component of the multiple components has changed its operating mode. In response to the detection, the control circuitry may modify at least one parameter of the following parameters to recover a portion of the first voltage margin: a power supply voltage magnitude and an operating frequency of at least a portion of the system. A magnitude of the modification may be based on an estimated difference between a first amount of dynamic power supply voltage loss before the change in operating mode and a second amount of dynamic power supply voltage loss after the change in operating mode.