公开(公告)号：US09824171B2

公开(公告)日：2017-11-21

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

公开(公告)号：US20170039299A1

公开(公告)日：2017-02-09

申请号：US14820223

申请日：2015-08-06

Applicant: Apple Inc.

Inventor： Harsha Krishnamurthy ,  Mridul Agarwal ,  Shyam Sundar Balasubramanian ,  Christopher S. Thomas ,  Rajat Goel ,  Rohit Kumar ,  Muthukumaravelu Velayoudame

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F17/5068

Abstract: In some embodiments, a register file circuit design process includes instructing an automated integrated circuit design program to generate a register file circuit design, including providing a cell circuit design and instructing the automated integrated circuit design program to generate a selection design, a pre-decode design, and a data gating design. The cell circuit design describes a plurality of selection circuits that have a particular arrangement. The selection design describes a plurality of replica circuits that include respective pluralities of selection circuits having the particular arrangement. The pre-decode design describes a pre-decode circuit configured to identify a plurality of entries identified by a portion of a write instruction. The data gating design describes data gating circuits configured, in response to the pre-decode circuit not identifying respective entries, to disable data inputs to respective write selection circuits connected to the respective entries.

Abstract translation: 在一些实施例中，寄存器文件电路设计过程包括指示自动集成电路设计程序产生寄存器文件电路设计，包括提供单元电路设计并指示自动化集成电路设计程序产生选择设计，预解码 设计和数据门控设计。 单元电路设计描述了具有特定布置的多个选择电路。 选择设计描述了包括具有特定布置的相应多个选择电路的多个复制电路。 预解码设计描述了预解码电路，其被配置为识别由写指令的一部分识别的多个条目。 数据门控设计描述了数据选通电路，其响应于未识别相应条目的预解码电路而配置，以禁止连接到各个条目的相应写入选择电路的数据输入。

公开(公告)号：US10372500B1

公开(公告)日：2019-08-06

申请号：US15046364

申请日：2016-02-17

Applicant: Apple Inc.

Inventor： Christopher S. Thomas ,  James N. Hardage, Jr. ,  Christopher M. Tsay

IPC: G06F9/50 ,  G06F9/48

Abstract: In some embodiments, a system includes a register file, a plurality of clock gating circuits, a free list circuit, and a register allocation adjustment circuit. The register file includes a plurality of registers. The clock gating circuits control receipt of a clock signal at respective regions of registers. The free list circuit performs multiple search operations in parallel to identify unallocated registers. The register allocation adjustment circuit implements a mapping between registers identified by the free list circuit and registers of the register file such that the multiple search operations identify whether registers of a first region are unallocated prior to identifying whether registers of a second region are unallocated. As a result, a region of the register file is less likely to be in use during a particular clock cycle and a clock gating circuit may prevent a clock signal from being received at the region.