公开(公告)号：US09454419B2

公开(公告)日：2016-09-27

申请号：US14016610

申请日：2013-09-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Yi Xu ,  James M. O'Connor

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/20

CPC classification number: G06F11/0727 ,  G06F11/2007 ,  G06F2201/85

Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.

Abstract translation: 提供了一种分区系统数据总线的方法和系统。 该方法可以包括分离包括一个或多个故障位的系统数据总线的一部分以形成分区数据总线。 此外，该方法包括在分区数据总线上传送数据以补偿由于系统数据总线中的一个或多个错误位导致的数据丢失。

公开(公告)号：US20150100739A1

公开(公告)日：2015-04-09

申请号：US14229404

申请日：2014-03-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe WANG ,  Yuan Xie ,  Yi Xu ,  Junli Gu ,  Ting Cao

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/127 ,  G06F12/121 ,  G06F2212/222

Abstract: A method, a system and a computer-readable medium for writing to a non-volatile cache memory are provided. The method maintains a write count associated with a set of memory locations. The method then selects a cache replacement policy based on the value of the write count and selecting a block within the set for writing data using the selected cache replacement policy. The selected cache replacement policy can introduce a randomized selection.

Abstract translation: 提供了用于写入非易失性高速缓冲存储器的方法，系统和计算机可读介质。 该方法保持与一组存储器位置相关联的写入计数。 然后，该方法基于写入计数的值来选择高速缓存替换策略，并且使用所选择的高速缓存替换策略来选择用于写入数据的集合内的块。 所选择的高速缓存替换策略可以引入随机选择。

公开(公告)号：US10956044B2

公开(公告)日：2021-03-23

申请号：US14891523

申请日：2013-05-16

Applicant: Advanced Micro Devices, Inc.

Inventor： Yi Xu ,  Nuwan S. Jayasena ,  Yuan Xie

IPC: G06F3/06 ,  G06F13/16 ,  G06F12/02 ,  G06F13/42 ,  G06F1/3203 ,  G11C7/10

Abstract: An integrated circuit device includes a memory controller coupleable to a memory. The memory controller to schedule memory accesses to regions of the memory based on memory timing parameters specific to the regions. A method includes receiving a memory access request at a memory device. The method further includes accessing, from a timing data store of the memory device, data representing a memory timing parameter specific to a region of the memory cell circuitry targeted by the memory access request. The method also includes scheduling, at the memory controller, the memory access request based on the data.

公开(公告)号：US10361175B2

公开(公告)日：2019-07-23

申请号：US15428536

申请日：2017-02-09

Applicant: Advanced Micro Devices, Inc.

Inventor： Yi Xu ,  Xing Hu ,  Yuan Xie

IPC: G06F17/50 ,  H01L25/07 ,  G06F1/329 ,  G06F9/48 ,  H01L25/065 ,  H01L23/528

Abstract: The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

公开(公告)号：US20150026511A1

公开(公告)日：2015-01-22

申请号：US14016610

申请日：2013-09-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Gabriel H. Loh ,  Yi Xu ,  James M. O'Connor

IPC: G06F11/07

CPC classification number: G06F11/0727 ,  G06F11/2007 ,  G06F2201/85

Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.

Abstract translation: 提供了一种分区系统数据总线的方法和系统。 该方法可以包括分离包括一个或多个故障位的系统数据总线的一部分以形成分区数据总线。 此外，该方法包括在分区数据总线上传送数据以补偿由于系统数据总线中的一个或多个错误位导致的数据丢失。

公开(公告)号：US20150019823A1

公开(公告)日：2015-01-15

申请号：US13942291

申请日：2013-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Zhe Wang ,  Junli Gu ,  Yi Xu

IPC: G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0804 ,  G06F12/0808 ,  G06F12/0864 ,  G06F12/12 ,  G06F12/123 ,  G06F12/126

Abstract: A cache includes a cache array and a cache controller. The cache array has a plurality of entries. The cache controller is coupled to the cache array. The cache controller evicts entries from the cache array according to a cache replacement policy. The cache controller evicts a first cache line from the cache array by generating a writeback request for modified data from the first cache line, and subsequently generates a writeback request for modified data from a second cache line if the second cache line is about to satisfy the cache replacement policy and stores data from a common locality as the first cache line.

Abstract translation: 高速缓存包括高速缓存阵列和高速缓存控制器。 高速缓存阵列具有多个条目。 缓存控制器耦合到高速缓存阵列。 高速缓存控制器根据高速缓存替换策略从高速缓存阵列中排除条目。 高速缓存控制器通过从第一高速缓存行产生对修改数据的回写请求，从高速缓冲存储器阵列中驱除第一高速缓存行，并且随后如果第二高速缓存行即将满足第二高速缓存行，则从第二高速缓存行生成对修改数据的回写请求 高速缓存替换策略并将来自公共位置的数据存储为第一高速缓存行。