Invention Grant
- Patent Title: Voltage droop mitigation in 3D chip system
-
Application No.: US15428536Application Date: 2017-02-09
-
Publication No.: US10361175B2Publication Date: 2019-07-23
- Inventor: Yi Xu , Xing Hu , Yuan Xie
- Applicant: Advanced Micro Devices, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Advanced Micro Devices, Inc.
- Current Assignee: Advanced Micro Devices, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Faegre Baker Daniels LLP
- Priority: CN201310659511 20131209
- Main IPC: G06F17/50
- IPC: G06F17/50 ; H01L25/07 ; G06F1/329 ; G06F9/48 ; H01L25/065 ; H01L23/528

Abstract:
The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.
Public/Granted literature
- US20170153916A1 VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM Public/Granted day:2017-06-01
Information query