公开(公告)号：US20050283483A1

公开(公告)日：2005-12-22

申请号：US11152091

申请日：2005-06-15

申请人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

发明人： Minoru Okamoto ,  Katsuhiko Ueda ,  Shirou Yoshioka ,  Tetsuji Kishi

IPC分类号： G06F9/445 ,  G06F13/00 ,  G06F15/00 ,  G06F17/30 ,  G06Q30/06 ,  G06Q50/00 ,  H04L29/08 ,  H04N7/173

CPC分类号： H04L67/303 ,  H04L67/04 ,  H04L67/18 ,  H04N7/17318

摘要： A terminal device transmits device information thereof and a request for acquiring information contents to a contents distribution device. The contents distribution device generates a request for distributing a program for materializing the information contents in the terminal device based on the information contents designated in the acquisition request and the device information, and transmits the distribution request to a program distribution device and transmits the device information to an inspection device. The program distribution device transmits the program in the distribution request to the inspection device. The inspection device inspects a materialization state of the information contents in the terminal device based on the program and the device information and transmits a result of the inspection to the program distribution device and the contents distribution device. The program distribution device transmits the program to the terminal device and the contents distribution device transmits the information contents to the terminal device only when the inspection result is favorable.

摘要翻译： 终端装置向内容发布装置发送其设备信息和获取信息内容的请求。 内容分发装置根据获取请求中指定的信息内容和设备信息生成分发用于实现终端装置中的信息内容的程序的请求，并将分发请求发送给节目发布装置，并发送装置信息 到检查装置。 程序分配装置将分发请求中的程序发送到检查装置。 检查装置基于程序和设备信息检查终端装置中的信息内容的实现状态，并将检查结果发送给程序发布装置和内容分发装置。 程序发布装置将程序发送到终端装置，并且内容分发装置仅在检查结果有利时才向终端装置发送信息内容。

公开(公告)号：US5497473A

公开(公告)日：1996-03-05

申请号：US90931

申请日：1993-07-14

申请人： Akira Miyoshi ,  Shirou Yoshioka

发明人： Akira Miyoshi ,  Shirou Yoshioka

IPC分类号： G06F12/08 ,  G06F12/02

CPC分类号： G06F12/0846

摘要： A signal cache memory controller which includes line for inputting an index section of an address is formed with a branch line which is intervened by an address delay circuit. In each of banks X and Y, a switching circuit selects the data which has been delayed in response to a select signal Sse being outputted as a cache-access address to be outputted to a tag memory. An address comparator compares a tag section of the address input through a signal line for inputting the tag section with a reference address output from the tag memory and outputs an coincidence signal if there is a coincidence therebetween. When the coincidence signal is generated and the select signal Sse is not generated, a bank-hit signal generating circuit generated a bank-hit signal Sbh, in response to which a select-signal generating circuit generates the select signal Sse. The circuit for controlling a cache memory which is divided into a plurality of banks enables the writing of data in the cache in every cycle.

摘要翻译： 包括用于输入地址的索引部分的行的信号高速缓冲存储器控制器形成有由地址延迟电路干预的分支线。 在每个存储体X和Y中，切换电路选择响应于输出的选择信号Sse被延迟的数据作为要输出到标签存储器的高速缓存访​​问地址。 地址比较器将通过用于输入标签部分的信号线输入的地址的标签部分与从标签存储器输出的参考地址进行比较，并且如果它们之间存在一致，则输出一致信号。 当产生符合信号并且不产生选择信号Sse时，存储体命中信号发生电路产生一个选通信号产生电路产生选择信号Sse的存储体命中信号Sbh。 用于控制被分成多个存储体的高速缓冲存储器的电路使得能够在每个周期中在高速缓存中写入数据。

公开(公告)号：US20090083530A1

公开(公告)日：2009-03-26

申请号：US11886868

申请日：2006-04-04

申请人： Osamu Nishijima ,  Shirou Yoshioka ,  Yukihiro Sasagawa ,  Kenichi Kawaguchi

发明人： Osamu Nishijima ,  Shirou Yoshioka ,  Yukihiro Sasagawa ,  Kenichi Kawaguchi

IPC分类号： G06F9/00

CPC分类号： G06F15/7867

摘要： A configuration information storage section (108) stores configuration information for allowing a reconfigurable module to execute a predetermined function. A CPU (100) configures attached reconfigurable modules (103 to 106) according to the number thereof by referencing the configuration information stored in the configuration information storage section (108).

摘要翻译： 配置信息存储部（108）存储用于允许可重构模块执行预定功能的配置信息。 CPU（100）通过参照存储在配置信息存储部（108）中的配置信息，根据其数量配置附加的可重配置模块（103〜106）。

公开(公告)号：US07287123B2

公开(公告)日：2007-10-23

申请号：US11137560

申请日：2005-05-26

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据 在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为 将数据存储到不同于第一种方式的条目中。

公开(公告)号：US20100095096A1

公开(公告)日：2010-04-15

申请号：US12526221

申请日：2008-06-27

申请人： Shirou Yoshioka

发明人： Shirou Yoshioka

IPC分类号： G06F9/30

CPC分类号： H04N5/85 ,  G11B27/34 ,  G11B2220/2562 ,  H04N5/765 ,  H04N21/42646 ,  H04N21/443

摘要： In an AV device control, from unit instructions (210, 220, 230) for executing a series of operations, input parts (211, 221, 231) for allowing user inputs to be inputted are respectively extracted and the extracted input parts (211, 221, 231) are concatenated as a first process, and execution parts (212, 222, 232) for operating the AV device according to the inputted user inputs are respectively extracted and the extracted execution parts (212, 222, 232) are concatenated as a second process. Then, the first process is arranged to be followed by the second process to constitute a macro instruction (240). In control using the macro instruction (240), after the user inputs required for executing the macro instruction are all inputted by the first process, the macro instruction by the second process is executed.

摘要翻译： 在AV设备控制中，从用于执行一系列操作的单元指令（210,220,230）中分别提取用于允许输入用户输入的输入部分（211,221,231），并且提取的输入部分 221,231）被级联为第一处理，并且分别提取用于根据所输入的用户输入操作AV设备的执行部分（212,222,232），并且提取的执行部分（212,222,232）被级联为 第二个过程。 然后，第一处理被布置成随后是第二处理以构成宏指令（240）。 在使用宏指令（240）的控制中，在通过第一处理全部输入执行宏指令所需的用户输入之后，执行第二处理的宏指令。

公开(公告)号：US20090271575A1

公开(公告)日：2009-10-29

申请号：US12498623

申请日：2009-07-07

申请人： Shirou YOSHIOKA

发明人： Shirou YOSHIOKA

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/084 ,  G06F12/0842 ,  G06F12/0864

摘要： A cache memory according to the present invention is a cache memory that has a set associative scheme and includes: a plurality of ways, each way being made up of entries, each entry holding data and a tag; a first holding unit operable to hold, for each way, a priority attribute that indicates a type of data to be preferentially stored in that way; a second holding unit which is included at least in a first way among the ways, and is operable to hold, for each entry of the first way, a data attribute that indicates a type of data held in that entry; and a control unit operable to perform replace control on the entries by prioritizing a way whose priority attribute held by the first holding unit matches a data attribute outputted from a processor, wherein when a cache miss occurs and in the case where (i) valid data is held in an entry of the first way among entries that belong to a set selected based on an address outputted from the processor, (ii) all of the following attributes match: the data attribute of the entry; the data attribute outputted from the processor; and the priority attribute of the first way, and (iii) an entry of a way other than the first way does not hold valid data, the entry being one of the entries that belong to the selected set, the control unit is further operable to store data into the entry of the way other than the first way.

摘要翻译： 根据本发明的高速缓冲存储器是具有集合关联方案的高速缓冲存储器，包括：多个方式，每个方式由条目组成，每个条目保存数据和标签; 第一保持单元，用于以每一方式保存指示以该方式优先存储的数据类型的优先级属性; 第二保持单元，其至少以所述方式中的第一方式被包括，并且可操作地对于所述第一方式的每个条目保存指示保存在所述条目中的数据类型的数据属性; 以及控制单元，其可操作以通过对由所述第一保持单元保持的优先级属性与从处理器输出的数据属性相匹配的方式来对所述条目执行替换控制，其中当发生高速缓存未命中时，以及（i）有效数据 在属于基于从处理器输出的地址选择的集合的条目之中的第一路径的条目中保存;（ii）所有以下属性都匹配：条目的数据属性; 从处理器输出的数据属性; 和所述第一方式的优先级属性，以及（iii）除了所述第一方式之外的方式的条目不保存有效数据，所述条目是属于所选集合的条目之一，所述控制单元还可操作为 将数据存储到不同于第一种方式的条目中。

公开(公告)号：US20090106798A1

公开(公告)日：2009-04-23

申请号：US12253705

申请日：2008-10-17

申请人： Hideaki NABATANI ,  Shirou YOSHIOKA

发明人： Hideaki NABATANI ,  Shirou YOSHIOKA

IPC分类号： H04N5/445 ,  G06F17/21

CPC分类号： G06F17/2223

摘要： A character string receiving device includes a reception unit for receiving character string data indicating a character string via unidirectional communication, and a character string processing unit for processing the character string data received by the reception unit.

摘要翻译： 字符串接收装置包括：接收单元，用于通过单向通信接收指示字符串的字符串数据;以及字符串处理单元，用于处理由接收单元接收的字符串数据。

公开(公告)号：US07120773B2

公开(公告)日：2006-10-10

申请号：US10701073

申请日：2003-11-05

申请人： Shirou Yoshioka ,  Hirofumi Kaneko

发明人： Shirou Yoshioka ,  Hirofumi Kaneko

IPC分类号： G06F12/02

CPC分类号： G06F12/1027 ,  G06F12/0238 ,  G06F12/0802 ,  G06F12/0804

摘要： A TLB provided in a memory management apparatus stores an entry for each logical page, and each entry holds an address of a physical page mapped to a corresponding logical page, an index showing the degradation degree of the physical page, and an index showing the access frequency to the logical page. The memory management apparatus accesses a physical page mapped to a desired logical page according to the data stored in the TLB, periodically exchanges the contents between a first physical page mapped to a specific logical page having a largest access frequency index and a second physical page having a smallest degradation index, and then maps the specific logical page to the second physical page. Through the physical page exchange and corresponding mapping process, accesses to each physical page are distributed, so that degradation in storage function is substantially equalized.

摘要翻译： 提供在存储器管理装置中的TLB存储每个逻辑页的条目，并且每个条目保存映射到相应逻辑页的物理页的地址，表示物理页的劣化程度的索引以及显示访问的索引 频率到逻辑页面。 存储器管理装置根据存储在TLB中的数据访问映射到期望逻辑页面的物理页面，周期性地交换映射到具有最大访问频率索引的特定逻辑页面的第一物理页面和具有最大访问频率索引的第二物理页面之间的内容， 最小的降级索引，然后将特定的逻辑页面映射到第二个物理页面。 通过物理页面交换和相应的映射过程，对每个物理页面的访问进行分发，从而大大平衡了存储功能的降级。

公开(公告)号：US5751374A

公开(公告)日：1998-05-12

申请号：US618610

申请日：1996-03-20

申请人： Kazuki Ninomiya ,  Shirou Yoshioka ,  Tamotsu Nishiyama

发明人： Kazuki Ninomiya ,  Shirou Yoshioka ,  Tamotsu Nishiyama

IPC分类号： H04N5/46 ,  H04N5/907 ,  H04N7/015 ,  H04N9/00 ,  H04N9/64 ,  H04N5/14

CPC分类号： H04N5/46 ,  H04N7/0152 ,  H04N9/642 ,  H04N5/907

摘要： A coprocessor is incorporated in a processor comprising a CPU, an instruction cache, a data memory, a bus controller, an interruption control section and a DMA controller. This coprocessor has a parallel sum-of-products arithmetic operation section, a comparator, an I/O register section, and a sum-of-products factor register section. A frame memory, provided on the input side, stores MUSE or NTSC signals digitized per pixel. The DMA is in control of the transfer of data between the input-side frame memory and the data memory as well as the transfer of data between a frame memory provided on the output side and the data memory. Pixel data stored in the data memory is processed according to broadcasting systems by the switching of sum-of-products factors on the basis of software.

摘要翻译： 协处理器被并入包括CPU，指令高速缓存，数据存储器，总线控制器，中断控制部分和DMA控制器的处理器中。 该协处理器具有并行产品总和运算部分，比较器，I / O寄存器部分和产品总和因子寄存器部分。 在输入侧提供的帧存储器存储每像素数字化的MUSE或NTSC信号。 DMA控制输入侧帧存储器和数据存储器之间的数据传送以及在输出侧提供的帧存储器与数据存储器之间的数据传送。 存储在数据存储器中的像素数据根据广播系统通过基于软件的乘积因子的切换进行处理。