公开(公告)号：US07577781B2

公开(公告)日：2009-08-18

申请号：US12155047

申请日：2008-05-29

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US07398346B2

公开(公告)日：2008-07-08

申请号：US11543878

申请日：2006-10-06

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

公开(公告)号：US5889971A

公开(公告)日：1999-03-30

申请号：US959913

申请日：1997-10-29

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US5483642A

公开(公告)日：1996-01-09

申请号：US311893

申请日：1994-09-26

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US5223459A

公开(公告)日：1993-06-29

申请号：US714670

申请日：1991-06-13

申请人： Shiro Odawara ,  Keiichi Ito ,  Kazushi Kobayashi

发明人： Shiro Odawara ,  Keiichi Ito ,  Kazushi Kobayashi

IPC分类号： B64F5/00 ,  E04B1/346 ,  E04H6/44

CPC分类号： B64F5/0009 ,  E04B1/346 ,  E04H6/44 ,  Y02P70/585

摘要： A working system for an aeroplane comprising a hangar for accommodating the aeroplane, a partition wall provided within the hangar for partitioning the hangar into a fuselage work area around a fuselage of the aeroplane and a main wing work area around a main wing, and working tables arranged in the fuselage work area. The partition wall is movable between a predetermined partitioning position and a retracted position allowing entrance and exit of the aeroplane. The working tables are movable within the fuselage work area separately from the partition wall.

摘要翻译： 一种用于飞机的工作系统，包括用于容纳飞机的机库，设置在机库内的分隔壁，用于将机库分隔成机身的机身周围的机身工作区域和主翼周围的主翼工作区域以及工作台 安排在机身工作区。 分隔壁可以在预定的分隔位置和允许飞机进出的缩回位置之间移动。 工作台可以在机身工作区域内与隔墙分开移动。

公开(公告)号：US20080071060A1

公开(公告)日：2008-03-20

申请号：US11629655

申请日：2005-09-09

申请人： Kazushi Kobayashi ,  Koji Beppu

发明人： Kazushi Kobayashi ,  Koji Beppu

IPC分类号： C08G67/00

CPC分类号： C08F2/24 ,  B01F17/005

摘要： A surfactant composition has good emulsifiability for monomer(s), and can provide a polymer emulsion (herein after simply called “the emulsion”) of good stability while decreasing coagulations of polymer particles in the emulsion. The surfactant composition contains the following components (A) and (B): (A) a reactive surfactant containing at least one polymerizable double-bond group and at least one ionic group in a molecule, and (B) a nitrogen compound insoluble or slightly soluble in ethanol. A weight ratio (A:B) of the component (A) to the component (B) is from 100:0.03 to 100:1.0.

摘要翻译： 表面活性剂组合物对于单体具有良好的乳化性，并且可以提供具有良好稳定性的聚合物乳液（这里简称为“乳液”），同时降低乳液中聚合物颗粒的凝结。 表面活性剂组合物含有下列组分（A）和（B）：（A）分子中含有至少一个可聚合双键基团和至少一个离子基团的反应性表面活性剂，（B）不溶于或稍微 溶于乙醇。 成分（A）与成分（B）的重量比（A:B）为100:0.03〜100:1.0。

公开(公告)号：US06907489B2

公开(公告)日：2005-06-14

申请号：US10787110

申请日：2004-02-27

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。

公开(公告)号：US5935231A

公开(公告)日：1999-08-10

申请号：US143985

申请日：1998-08-31

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/00

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

公开(公告)号：US5890220A

公开(公告)日：1999-03-30

申请号：US455632

申请日：1995-05-31

申请人： Tetsuya Mochida ,  Hitoshi Kawaguchi ,  Kazushi Kobayashi ,  Ichiharu Aburano ,  Takanori Ishikawa

发明人： Tetsuya Mochida ,  Hitoshi Kawaguchi ,  Kazushi Kobayashi ,  Ichiharu Aburano ,  Takanori Ishikawa

IPC分类号： G06F12/10 ,  G06F13/28

CPC分类号： G06F12/1081 ,  G06F13/28

摘要： In a computer system having an address converter for DMA (direct memory access), an address conversion apparatus in which a memory area to be accessed by the DMA can be accessed at high speed from a CPU. A "DMA address conversion area" is defined in a memory space, and address conversion means in the mode of accessing the DMA address conversion area is so constructed that, when the area has been accessed from the CPU, a physical address is generated in accordance with the address conversion routine of the DMA address conversion means or converter, so as to access a main storage. The memory area to be accessed by the DMA can be quickly accessed from the CPU without requiring such an operation as especially accessing the control ware of the address converter or producing the physical address under the management of a program run on the CPU.

摘要翻译： 在具有用于DMA（直接存储器访问）的地址转换器的计算机系统中，可以从CPU高速访问由DMA访问的存储器区域的地址转换装置。 在存储器空间中定义了“DMA地址转换区域”，并且访问DMA地址转换区域的方式中的地址转换装置的结构使得当从CPU访问该区域时，根据 利用DMA地址转换装置或转换器的地址转换程序，以访问主存储器。 可以从CPU快速访问由DMA访问的存储器区域，而不需要特别访问地址转换器的控制器或在CPU上运行的程序的管理下产生物理地址的操作。

公开(公告)号：US5668956A

公开(公告)日：1997-09-16

申请号：US449088

申请日：1995-05-24

申请人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

发明人： Koichi Okazawa ,  Koichi Kimura ,  Hitoshi Kawaguchi ,  Ichiharu Aburano ,  Kazushi Kobayashi ,  Tetsuya Mochida

IPC分类号： G06F13/16 ,  G06F12/00 ,  G06F13/36 ,  G06F13/40 ,  G06F13/14

CPC分类号： G06F13/4022 ,  G06F13/4027

摘要： A processor bus linked with at least a processor, a memory bus linked with a main memory, and a system bus linked with at least an input/output device are connected to a three-way connection control system. The control system includes a bus-memory connection controller connected to address buses and control buses respectively of the processor, memory, and system buses to transfer address and control signals therebetween. The control system further includes a data path switch connected to data buses respectively of the processor, memory, and system buses to transfer data via the data buses therebetween depending on the data path control signal.

摘要翻译： 与至少一个处理器连接的处理器总线，与主存储器连接的存储器总线以及与至少一个输入/输出设备链接的系统总线连接到三路连接控制系统。 控制系统包括总线存储器连接控制器，分别连接到处理器，存储器和系统总线的地址总线和控制总线，以在它们之间传送地址和控制信号。 控制系统还包括连接到处理器，存储器和系统总线的数据总线的数据通路开关，以根据数据路径控制信号经由其间的数据总线传输数据。