公开(公告)号：US20170054070A1

公开(公告)日：2017-02-23

申请号：US15146355

申请日：2016-05-04

申请人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

发明人： Jung-Hoon Bak ,  Myoung-Su Son ,  Jae-Chul Shim ,  Gwan-Hyeob Koh ,  Yoon-Jong Song

IPC分类号： H01L43/02 ,  H01L43/10 ,  H01L43/12 ,  H01L43/08

CPC分类号： H01L43/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

摘要： In a method of manufacturing an MRAM device, a memory unit including a lower electrode, an MTJ structure and an upper electrode sequentially stacked is formed on a substrate. A protective layer structure including a capping layer, a sacrificial layer and an etch stop layer sequentially stacked is formed on the substrate to cover the memory unit. An insulating interlayer is formed on the protective layer structure. The insulating interlayer is formed to form an opening exposing the protective layer structure. The exposed protective layer structure is partially removed to expose the upper electrode. A wiring is formed on the exposed upper electrode to fill the opening.

摘要翻译： 在制造MRAM器件的方法中，在衬底上形成包括下电极，MTJ结构和顺序层叠的上电极的存储单元。 在衬底上形成包括依次堆叠的覆盖层，牺牲层和蚀刻停止层的保护层结构以覆盖存储单元。 在保护层结构上形成绝缘中间层。 形成绝缘中间层以形成露出保护层结构的开口。 暴露的保护层结构被部分去除以暴露上电极。 在暴露的上电极上形成布线以填充开口。

公开(公告)号：US20110080820A1

公开(公告)日：2011-04-07

申请号：US12894248

申请日：2010-09-30

申请人： Jae-chul SHIM ,  Hae-Jung LEE

发明人： Jae-chul SHIM ,  Hae-Jung LEE

IPC分类号： G11B27/36

CPC分类号： G11B5/09 ,  G11B20/10009 ,  G11B20/1037 ,  G11B20/10481 ,  G11B20/1258 ,  G11B2020/1242 ,  G11B2020/1289 ,  G11B2020/1292 ,  G11B2220/2516

摘要： A data storage device determines a zone layout based on a quality evaluation factor. The zone layout is designed such that a measurement value of the quality evaluation factor for each track in each zone is within a range between a predetermined upper limit and a predetermined lower limit and a maximum amount of variation of the measurement value within each zone is substantially equal to a difference between the upper limit and the lower limit.

摘要翻译： 数据存储设备基于质量评估因子确定区域布局。 区域布局被设计成使得每个区域中的每个轨道的质量评估因子的测量值在预定上限和预定下限之间的范围内，并且每个区域内的测量值的最大变化量基本上 等于上限和下限之间的差值。

公开(公告)号：US20170069684A1

公开(公告)日：2017-03-09

申请号：US15157403

申请日：2016-05-17

申请人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

发明人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

CPC分类号： H01L27/222 ,  H01L43/12

摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

摘要翻译： 制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。 通过蚀刻停止层和第一绝缘中间层形成下电极。 在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。 通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。 第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。