公开(公告)号：US06735689B1

公开(公告)日：2004-05-11

申请号：US09562061

申请日：2000-05-01

申请人： Thomas W. S. Thomson ,  Jack Choquette

发明人： Thomas W. S. Thomson ,  Jack Choquette

IPC分类号： G06F932

CPC分类号： G06F9/30058 ,  G06F9/3017 ,  G06F9/322

摘要： Penalty for taking branch in pipelined processor is reduced by pre-calculating target of conditional branch before branch is encountered, thereby effectively converting branches to jumps. During program execution, pipeline penalty is reduced effectively to that of unconditional jump. Offset bits are replaced in a conditional branch with index bits based on addition of offset bits and a program counter value. Scheme reduces need for cycle to calculate target of taken branch. Scheme may be applied during cache fill or dead cycle when taken branch is read from pipelined cache.

摘要翻译： 在流水线处理器中采取分支的处罚方式是通过在分支之前预先计算条件分支的目标，从而有效地将分支转换为跳转。 在程序执行过程中，管道损失有效地降低到无条件跳转。 偏移位在带有索引位的条件分支中被替换，该偏移位基于偏移位的加法和程序计数器值。 方案减少了循环的需求，以计算采取分支的目标。 当从流水线缓存读取分支时，可以在缓存填充或死循环期间应用方案。

公开(公告)号：US08522000B2

公开(公告)日：2013-08-27

申请号：US12569831

申请日：2009-09-29

申请人： Michael C. Shebanow ,  Jack Choquette ,  Brett W. Coon ,  Steven J. Heinrich ,  Aravind Kalaiah ,  John R. Nickolls ,  Daniel Salinas ,  Ming Y. Siu ,  Tommy Thorn ,  Nicholas Wang

发明人： Michael C. Shebanow ,  Jack Choquette ,  Brett W. Coon ,  Steven J. Heinrich ,  Aravind Kalaiah ,  John R. Nickolls ,  Daniel Salinas ,  Ming Y. Siu ,  Tommy Thorn ,  Nicholas Wang

IPC分类号： G06F9/00

CPC分类号： G06F9/327 ,  G06F9/3851 ,  G06F9/3861

摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.

摘要翻译： 陷阱处理器架构被并入到诸如GPU的并行处理子系统中。 陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

公开(公告)号：US20130179662A1

公开(公告)日：2013-07-11

申请号：US13348544

申请日：2012-01-11

申请人： Jack CHOQUETTE ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

发明人： Jack CHOQUETTE ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

IPC分类号： G06F9/30 ,  G06F9/312 ,  G06F9/38

CPC分类号： G06F9/3887 ,  G06F9/3851

摘要： An address divergence unit detects divergence between threads in a thread group and then separates those threads into a subset of non-divergent threads and a subset of divergent threads. In one embodiment, the address divergence unit causes instructions associated with the subset of non-divergent threads to be issued for execution on a parallel processing unit, while causing the instructions associated with the subset of divergent threads to be re-fetched and re-issued for execution.

摘要翻译： 地址发散单元检测线程组中的线程之间的差异，然后将这些线程分成非发散线程的子集和发散线程的子集。 在一个实施例中，地址发散单元导致与非发散线程的子集相关联的指令用于在并行处理单元上执行，同时引起与分支线程的子集相关联的指令被重新获取并重新发布 执行。

公开(公告)号：US20110078427A1

公开(公告)日：2011-03-31

申请号：US12569831

申请日：2009-09-29

申请人： Michael C. Shebanow ,  Jack Choquette ,  Brett W. Coon ,  Steven J. Heinrich ,  Aravind Kalaiah ,  John R. Nickolls ,  Daniel Salinas ,  Ming Y. Siu ,  Tommy Thorn ,  Nicholas Wang

发明人： Michael C. Shebanow ,  Jack Choquette ,  Brett W. Coon ,  Steven J. Heinrich ,  Aravind Kalaiah ,  John R. Nickolls ,  Daniel Salinas ,  Ming Y. Siu ,  Tommy Thorn ,  Nicholas Wang

IPC分类号： G06F9/38

CPC分类号： G06F9/327 ,  G06F9/3851 ,  G06F9/3861

摘要： A trap handler architecture is incorporated into a parallel processing subsystem such as a GPU. The trap handler architecture minimizes design complexity and verification efforts for concurrently executing threads by imposing a property that all thread groups associated with a streaming multi-processor are either all executing within their respective code segments or are all executing within the trap handler code segment.

摘要翻译： 陷阱处理器架构被并入到诸如GPU的并行处理子系统中。 陷阱处理器架构通过强加与流式多处理器相关联的所有线程组都在其各自的代码段内执行或全部在陷阱处理程序代码段内执行的属性来最小化并发执行线程的设计复杂性和验证工作。

公开(公告)号：US09606808B2

公开(公告)日：2017-03-28

申请号：US13348544

申请日：2012-01-11

申请人： Jack Choquette ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

发明人： Jack Choquette ,  Xiaogang Qiu ,  Jeff Tuckey ,  Michael (Ming Yiu) Siu ,  Robert J. Stoll ,  Olivier Giroux

IPC分类号： G06F9/38

CPC分类号： G06F9/3887 ,  G06F9/3851

摘要： A computing device detects divergences between threads in a thread group executing on a parallel processing unit. The computing device includes an address divergence unit that identifies a subset of non-divergent threads included in the thread group. The address divergence unit stores instructions related to the subset of non-divergent threads in a multi-issue queue. The address divergence unit causes the instructions related to the subset of non-divergent threads to be retrieved from the multi-issue queue when the parallel processing unit is available. The address divergence unit causes the subset of non-divergent threads to be issued for execution on the parallel processing unit. The address divergence unit repeats the identifying, storing, and causing steps for the remaining threads in the thread group that are not included in the subset of non-divergent threads.

公开(公告)号：US06708282B1

公开(公告)日：2004-03-16

申请号：US09654759

申请日：2000-09-05

申请人： Dominic Paul McCarthy ,  Jack Choquette

发明人： Dominic Paul McCarthy ,  Jack Choquette

IPC分类号： G06F1342

CPC分类号： G06F9/52

摘要： In complex systems, the arrival of data to a computation component is difficult to predict. A method of synchronizing the initiation of computation with the reception of its input data is disclosed. The method allows the input data and computation initiation commands to arrive in any order. The method is dynamically adjustable allowing for varying numbers of data inputs.

摘要翻译： 在复杂的系统中，难以预测数据到计算组件的到来。 公开了一种使计算开始与其输入数据的接收同步的方法。 该方法允许输入数据和计算启动命令以任何顺序到达。 该方法可动态调整，允许不同数量的数据输入。