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19 条记录 (耗时 0.013 秒)

    Causality-based memory ordering in a multiprocessing environment
    12.
    发明授权
    Causality-based memory ordering in a multiprocessing environment 有权

    公开(公告)号：US06681320B1

    公开(公告)日：2004-01-20

    申请号：US09474527

    申请日：1999-12-29

    申请人： Deborah T. Marr

    发明人： Deborah T. Marr

    IPC分类号： G06F9312

    CPC分类号： G06F12/0815

    摘要： Causality-based memory ordering in a multiprocessing environment. A disclosed embodiment includes a plurality of processors and arbitration logic coupled to the plurality of processors. The processors and arbitration logic maintain processor consistency yet allow stores generated in a first order by any two or more of the processors to be observed consistent with a different order of stores by at least one of the other processors. Causality monitoring logic coupled to the arbitration logic monitors any causal relationships with respect to observed stores.

    ESTABLISHING THREAD PRIORITY IN A PROCESSOR OR THE LIKE
    13.
    发明申请
    ESTABLISHING THREAD PRIORITY IN A PROCESSOR OR THE LIKE 有权
    在加工商或类似的环境中建立螺纹优先级

    公开(公告)号：US20120023502A1

    公开(公告)日：2012-01-26

    申请号：US13250175

    申请日：2011-09-30

    申请人： Deborah T. MARR

    发明人： Deborah T. MARR

    IPC分类号： G06F9/50 ,  G06F9/46

    CPC分类号： G06F9/4881 ,  G06F9/5011 ,  G06F2209/507

    摘要： In a multi-threaded processor, one or more variables are set up in memory (e.g., a register) to indicate which of a plurality of executable threads has a higher priority. Once the variable is set, several embodiments are presented for granting higher priority processing to the designated thread. For example, more instructions from the higher priority thread may be executed as compared to the lower priority thread. Also, a higher priority thread may be given comparatively more access to a given resource, such as memory or a bus.

    摘要翻译： 在多线程处理器中，在存储器（例如，寄存器）中设置一个或多个变量，以指示多个可执行线程中的哪一个具有较高优先级。 一旦设置了变量，就呈现了几个实施例，用于向指定的线程授予更高优先级的处理。 例如，与较低优先级线程相比，可以执行来自较高优先级线程的更多指令。 此外，可以给予较高优先级的线程相对更多地访问诸如存储器或总线的给定资源。

    Method and apparatus for pausing execution in a processor or the like
    15.
    发明授权
    Method and apparatus for pausing execution in a processor or the like 有权
    用于在处理器等中暂停执行的方法和装置

    公开(公告)号：US06671795B1

    公开(公告)日：2003-12-30

    申请号：US09489130

    申请日：2000-01-21

    申请人： Deborah T. Marr ,  Dion Rodgers

    发明人： Deborah T. Marr ,  Dion Rodgers

    IPC分类号： G06F948

    CPC分类号： G06F9/3869 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/52

    摘要： A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

    摘要翻译： 描述用于暂停从线程执行指令的方法和装置。 在一个实施例中，暂停指令被实现为两个指令或微指令：SET指令和READ指令。 当为给定的线程检索SET标志时，SET指令在存储器中设置一个Bit标志，指示线程的执行已暂停。 SET指令放在流水线中执行。 然而，针对该线程的以下READ指令被阻止进入流水线，直到SET指令被执行并退出（导致清除Bit标志）。 一旦Bit标志被清除，READ指令被放置在流水线中才能执行。 在一个线程的处理暂停的时间内，其他线程的执行可能会继续。

    Method and apparatus for pausing execution in a processor or the like
    16.
    发明授权
    Method and apparatus for pausing execution in a processor or the like 有权
    用于在处理器等中暂停执行的方法和装置

    公开(公告)号：US07451296B2

    公开(公告)日：2008-11-11

    申请号：US10728962

    申请日：2003-12-08

    申请人： Deborah T. Marr ,  Dion Rodgers

    发明人： Deborah T. Marr ,  Dion Rodgers

    IPC分类号： G06F7/38

    CPC分类号： G06F9/3869 ,  G06F9/30083 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3851 ,  G06F9/52

    摘要： A method and apparatus for pausing execution of instructions from a thread is described. In one embodiment, a pause instruction is implemented as two instructions or microinstructions: a SET instruction and a READ instruction. When a SET flag is retrieved for a given thread, the SET instruction sets a Bit flag in memory indicating that execution for the thread has been paused. The SET instruction is placed in the pipeline for execution. The following READ instruction for that thread, however, is prevented from entering the pipeline until, the SET instruction is executed and retired (resulting in a clearing of the Bit flag). Once the Bit flag has been cleared, the READ instruction is placed in the pipeline for execution. During the time that processing of one thread is paused, the execution of other threads may continue.

    摘要翻译： 描述用于暂停从线程执行指令的方法和装置。 在一个实施例中，暂停指令被实现为两个指令或微指令：SET指令和READ指令。 当为给定的线程检索SET标志时，SET指令在存储器中设置一个Bit标志，指示线程的执行已暂停。 SET指令放在流水线中执行。 然而，针对该线程的以下READ指令被阻止进入流水线，直到SET指令被执行并退出（导致清除Bit标志）。 一旦Bit标志被清除，READ指令被放置在流水线中才能执行。 在一个线程的处理暂停的时间内，其他线程的执行可能会继续。