公开(公告)号：US07080191B2

公开(公告)日：2006-07-18

申请号：US10034834

申请日：2001-12-27

申请人： Brett W. Murdock ,  Craig D. Shaw ,  Jeremy A. Jacobson

发明人： Brett W. Murdock ,  Craig D. Shaw ,  Jeremy A. Jacobson

IPC分类号： G06F12/00

CPC分类号： G06F12/0607

摘要： A system for accessing memory devices includes a processing module coupled to a set of outputs and memory operably coupled to the processing module. The memory stores operational instructions that cause the processing module to perform a plurality of operations. A first one of the plurality of operations includes utilizing a first output to provide a first data lane enable to facilitate accessing of a portion of a first memory storage location associated with a first memory address when in a first mode of operation. A second one of the plurality of operations includes utilizing the first output to provide an address bit of a second memory address to facilitate designation of a second memory storage location when in a second mode of operation.

公开(公告)号：US06954821B2

公开(公告)日：2005-10-11

申请号：US10631167

申请日：2003-07-31

申请人： Michael D. Fitzsimmons ,  William C. Moyer ,  Brett W. Murdock

发明人： Michael D. Fitzsimmons ,  William C. Moyer ,  Brett W. Murdock

IPC分类号： G06F13/00 ,  G06F13/40

CPC分类号： G06F13/4022 ,  Y02D10/14 ,  Y02D10/151

摘要： A crossbar switch (12) arbitrates for access from multiple bus masters (14, 16, 18, 20 and 22) to multiple addressed slave ports (3 and 4) that have overlapping address ranges. In one form, the address ranges are the same address range. The crossbar switch (12) uses shared slave port control circuitry (48), configuration registers (46) and slave port arbiter logic (34, 36, 38, 40, 42 and 44) to arbitrate for access when all the addressed ports are busy. A determination is made as to whether new access requests are higher or lower in priority than existing accesses. A determination on where to direct a new access request is made based upon a prediction of which of certain multiple accesses will complete first based on various factors including the number of data beats requested as well as wait state information. In one mode, the wait state information is determined dynamically.

摘要翻译： 交叉开关（12）仲裁用于从多个总线主机（14,16,18,20和22）到具有重叠地址范围的多个寻址从端口（3和4）的访问。 在一种形式中，地址范围是相同的地址范围。 当所有寻址端口都忙时，交叉开关（12）使用共享从端口控制电路（48），配置寄存器（46）和从端口仲裁器逻辑（34,36,38,40,42和44）仲裁访问 。 确定新的访问请求是否比现有访问的优先级更高或更低。 基于对包括所请求的数据跳动的数量以及等待状态信息的各种因素的预测，首先将确定某个多个访问中的哪一个将首先完成，从而确定何时引导新的访问请求。 在一种模式中，动态地确定等待状态信息。

公开(公告)号：US07865897B2

公开(公告)日：2011-01-04

申请号：US11347103

申请日：2006-02-03

申请人： Benjamin C. Eckermann ,  Brett W. Murdock ,  William C. Moyer

发明人： Benjamin C. Eckermann ,  Brett W. Murdock ,  William C. Moyer

IPC分类号： G06F9/46

CPC分类号： G06F13/14 ,  G06F13/36

摘要： A method includes receiving, at an interconnect, a first transaction request from a first requesting module. The first transaction request includes a request to utilize at least one system resource accessible via the interconnect. The method further includes determining potential interferences at the interconnect expected to occur as a result of a utilization of the at least one system resource by the first requesting module and initiating processing of the first transaction request at the interconnect. The method additionally includes authorizing processing of a second transaction request from a second requesting module during the processing of the first transaction request based on the determined potential interferences.

摘要翻译： 一种方法包括在互连处从第一请求模块接收第一事务请求。 第一交易请求包括利用经由互连可访问的至少一个系统资源的请求。 该方法还包括确定作为由第一请求模块利用至少一个系统资源并且在互连处开始处理第一事务请求的结果期望发生的互连处的潜在干扰。 该方法另外包括基于所确定的潜在干扰，在第一交易请求的处理期间授权处理来自第二请求模块的第二交易请求。

公开(公告)号：US07013357B2

公开(公告)日：2006-03-14

申请号：US10660845

申请日：2003-09-12

申请人： Brett W. Murdock ,  William C. Moyer

发明人： Brett W. Murdock ,  William C. Moyer

IPC分类号： G06F13/38

CPC分类号： G06F13/4031 ,  G06F13/4022

摘要： An arbitration control circuit (11) for arbitrating access to a slave device (4) by a plurality of master devices (2, 3) includes an undefined length burst (ULB) arbitration logic circuit (12). The ULB arbitration logic circuit (12) includes a counter (26) and a control register (24). The control register (24) stores a predetermined value. During a ULB access of the slave device (4), the counter (26) is loaded with the predetermined value and is decremented for each beat of the undefined length burst access. Arbitration of the slave device (4) is only allowed after the predetermined number of access beats during the undefined length burst access.

摘要翻译： 用于仲裁由多个主设备（2,3）访问从设备（4）的仲裁控制电路（11）包括未定义的长度突发（ULB）仲裁逻辑电路（12）。 ULB仲裁逻辑电路（12）包括计数器（26）和控制寄存器（24）。 控制寄存器（24）存储预定值。 在从设备（4）的ULB接入期间，计数器（26）被加载预定值，并且对于未定义的长度突发存取的每个节拍而递减。 从设备（4）的仲裁只有在未定义的长度突发存取期间的预定数量的访问节拍之后才允许。