公开(公告)号：US5816673A

公开(公告)日：1998-10-06

申请号：US730470

申请日：1996-10-11

Applicant: James P. Sauer ,  George J. Scholhamer ,  William C. Galloway

Inventor： James P. Sauer ,  George J. Scholhamer ,  William C. Galloway

IPC: G06F1/16 ,  G06F1/18 ,  H05K7/04 ,  A47B81/00 ,  H05K7/10

CPC classification number: G06F1/184 ,  G06F1/187 ,  G06F1/188

Abstract: A modular computer chassis constructed with a center pluggable interface adapted for the modular mounting of components on opposite sides thereof. The chassis includes frontal and rear regions which are open and adapted for receipt of modular computer components therein for direct coupling to the center pluggable interface. An isolation frame is also provided within the chassis for physically and electrically isolating select components therein one from the other. A slidable mounting array is also provided for facilitating flexibility in the mounting of half height and one-third height disk drives adjacent to the center pluggable interface for flexibility in the design and utilization of the chassis of the present invention.

Abstract translation: 一个模块化的计算机机箱，其中央可插拔接口适用于组件安装在其相对侧上。 底盘包括前部区域和后部区域，该区域是敞开的并且适于在其中接收模块化计算机部件，用于直接联接到中心可插接口。 隔离框架还设置在底盘内，用于物理和电气隔离其中一个选择部件。 还提供了可滑动的安装阵列，以便于在靠近中心可插拔接口的情况下安装半高和三分之一高度磁盘驱动器的灵活性，以便灵活地设计和利用本发明的底盘。

公开(公告)号：US5797003A

公开(公告)日：1998-08-18

申请号：US91134697

申请日：1997-08-14

Applicant: COMPAQ COMPUTER CORP

Inventor： VOCE MAURICE F

IPC: G06F3/02 ,  G06F1/00 ,  G06F3/048 ,  G06F3/14 ,  G06F9/455 ,  G06F9/50

CPC classification number: G06F9/45537 ,  G06F9/44578

公开(公告)号：US5796854A

公开(公告)日：1998-08-18

申请号：US810432

申请日：1997-03-04

Applicant: Mitchell A. Markow

Inventor： Mitchell A. Markow

IPC: G06F1/16 ,  H04R1/02 ,  H04R5/02 ,  H04R7/04 ,  H04R7/06 ,  H04R17/00 ,  H04R25/00

CPC classification number: G06F1/1616 ,  G06F1/1688 ,  H04R5/02 ,  H04R1/028 ,  H04R17/00 ,  H04R2205/022 ,  H04R2499/15 ,  H04R7/04 ,  H04R7/06

Abstract: A speaker system for use in a thin film video monitor apparatus is disclosed. The video monitor apparatus includes a thin film video display panel as well as a stiffening panel adjacent to the thin film video display panel. Next, a plurality of piezo speaker transducers are attached to one of the sides of the stiffening panel. The stiffening panel typically is composed of a material such as aluminum honeycomb sheets or a polycarbonate sheet. Other materials for use as the stiffener may include magnesium shells or ABS plastic. The speakers are defined so that a first sound channel and a second sound channel are provided, and these sound channels can define a left and right channel for proper stereo imaging. Between the video monitor and the stiffening panel is located an electromagnetic interference (EMI) shield. Further, a transmission line is provided to connect a first piezo transducer to a second piezo transducer in such a way so that frequency overlap can occur between the two transducers based upon the transmission line distance defined for the first piezo transducer and for the second piezo transducer. Further, the transmission line may have the same distance between both speakers where frequency overlap is not a concern. The stiffening panel is provided to increase the mobile energy in the lower frequencies during operation.

Abstract translation: 公开了一种用于薄膜视频监视器装置的扬声器系统。 视频监视器装置包括薄膜视频显示面板以及与薄膜视频显示面板相邻的加强板。 接下来，多个压电扬声器换能器附接到加强板的一侧。 加强板通常由铝蜂窝片或聚碳酸酯片等材料构成。 用作加强筋的其它材料可包括镁壳或ABS塑料。 扬声器被定义为使得提供第一声道和第二声道，并且这些声道可以定义用于正确立体声成像的左右声道。 在视频监视器和加强板之间设有电磁干扰（EMI）屏蔽。 此外，传输线被提供以将第一压电换能器连接到第二压电换能器，使得基于为第一压电换能器和第二压电换能器定义的传输线距离，两个换能器之间可能发生频率重叠 。 此外，传输线可以在两个扬声器之间具有相同的距离，其中不重视频率重叠。 提供加强板以在操作期间增加较低频率下的移动能量。

公开(公告)号：US5771349A

公开(公告)日：1998-06-23

申请号：US788433

申请日：1997-01-28

Applicant: Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

Inventor： Jose J. Picazo, Jr. ,  Paul Kakul Lee ,  Robert P. Zager

IPC: G06F13/00 ,  H04L12/24 ,  H04L12/44 ,  H04L12/46 ,  H04L12/56 ,  H04L29/06 ,  G06F12/14 ,  H04L9/00

CPC classification number: H04L41/26 ,  H04L12/44 ,  H04L12/4616 ,  H04L12/462 ,  H04L12/4625 ,  H04L29/06 ,  H04L41/0213 ,  H04L41/046 ,  H04L49/351 ,  H04L49/90 ,  H04L49/901 ,  H04L63/0209 ,  H04L63/083 ,  H04L49/201 ,  H04L49/25 ,  H04L49/254 ,  H04L49/3018 ,  H04L49/357 ,  H04L49/557

Abstract: A hub circuit with an integrated bridge circuit carried out in software including a switch for bypassing the bridge process such that the two bridged networks effectively become one network. An in-band management process in software is disclosed which receives and executes network management commands received as data packets from the LANs coupled to the integrated hub/bridge. Also, hardware and software to implement an isolate mode where data packets which would ordinarily be transferred by the bridge process are not transferred except in-band management packets are transferred to the in-band management process regardless of which network from which they arrived. Also disclosed, a packet switching machine having shared high-speed memory with multiple ports, one port coupled to a plurality of LAN controller chips coupled to individual LAN segments and an Ethernet microprocessor that sets up and manages a receive buffer for storing received packets and transferring pointers thereto to a main processor. The main processor is coupled to another port of the memory and analyzes received packets for bridging to other LAN segments or forwarding to an SNMP agent. The main microprocessor and the Ethernet processor coordinate to manage the utilization of storage locations in the shared memory. Another port is coupled to an uplink interface to higher speed backbone media such as FDDI, ATM etc. Speeds up to media rate are achieved by only moving pointers to packets around in memory as opposed to the data of the packets itself. A double password security feature is also implemented in some embodiments to prevent accidental or intentional tampering with system configuration settings.

公开(公告)号：US5754406A

公开(公告)日：1998-05-19

申请号：US659004

申请日：1996-06-04

Applicant: Thomas T. Hardt ,  Karl N. Walker

Inventor： Thomas T. Hardt ,  Karl N. Walker

IPC: G06F1/18 ,  H05K7/14 ,  H05K5/00

CPC classification number: G06F1/185 ,  G06F1/184 ,  G06F1/186 ,  H05K7/1405

Abstract: A card guide assembly for isolating printed circuit boards from each other during insertion and removal from a mounting array. The assembly includes first and second isolation channels that are configured to permit the receipt of a variety of PC board sizes therein and a securement cap for receipt thereover. The cap may be adjustably positioned within the isolation channels for establishing a secured mounting for a variety of PC board sizes. A locking mechanism is provided between the cap and the channels for secured engagement therebetween. The channels are mounted on opposite sides of the PC board connector region permitting conventional mounting of the PC board into a mounting connector.

Abstract translation: 一种用于在从安装阵列插入和移除期间将印刷电路板彼此隔离的卡引导组件。 组件包括被配置为允许其中接收各种PC板尺寸的第一和第二隔离通道和用于在其上接收的固定帽。 盖可以可调节地定位在隔离通道内，以建立用于各种PC板尺寸的固定安装。 在盖和通道之间提供锁定机构，以在它们之间固定接合。 通道安装在PC板连接器区域的相对侧，允许将PC板常规安装到安装连接器中。

公开(公告)号：US5666359A

公开(公告)日：1997-09-09

申请号：US560531

申请日：1995-11-17

Applicant: Arthur T. Bennett ,  K. Arlan Harris

Inventor： Arthur T. Bennett ,  K. Arlan Harris

IPC: G06F13/00 ,  H04L12/413 ,  H04L12/44 ,  H04L12/46 ,  H04L12/56 ,  H04L29/06 ,  H04J3/22

CPC classification number: H04L29/06 ,  H04L12/44 ,  H04L12/462 ,  H04L12/5693 ,  H04L47/6225 ,  H04L49/90 ,  H04L49/9063 ,  H04L12/4625 ,  H04L69/08 ,  H04L69/18

Abstract: A network (10) includes a repeater (12) that can service data devices that operate using different communications protocols. The data devices (18, 20, 22) couple to the ports (34) of the repeater (12), and operate using a first communications protocol in a first domain (14). The data devices (26, 28, 30) also couple to the ports (34) of the repeater (12) and operate using a second communications protocol in a second domain (16). Information on the operation of a port (34) may be displayed using one port indicator (202) or two port indicators (300, 302).

Abstract translation: 网络（10）包括可以为使用不同通信协议操作的数据设备提供服务的中继器（12）。 数据设备（18,20,22）耦合到中继器（12）的端口（34），并且使用第一域（14）中的第一通信协议进行操作。 数据设备（26,28,30）还耦合到中继器（12）的端口（34），并且在第二域（16）中使用第二通信协议进行操作。 可以使用一个端口指示器（202）或两个端口指示器（300,302）来显示关于端口（34）的操作的信息。

公开(公告)号：US5499184A

公开(公告)日：1996-03-12

申请号：US188095

申请日：1994-01-28

Applicant: George F. Squibb

Inventor： George F. Squibb

IPC: H02M3/335

CPC classification number: H02M3/33523

Abstract: A power switch circuit including a small signal transformer and a low power oscillator for detecting the power switch while isolating it from the primary of the power supply. When the power switch is off, or is otherwise pressed to turn off the power supply, the oscillator charges a capacitor. A sensing and control circuit coupled to the oscillator and capacitor grounds a vital signal of the power supply keeping the power supply turned off. In one embodiment, when the switch is turned on, it shorts the signal transformer disabling the oscillator, so that the capacitor is discharged and the sensing and control circuit releases the vital signal. In another embodiment, the power switch momentarily disables the oscillator and discharges the capacitor, so that the sensing and control circuit toggles a flip-flop circuit to turn on the power supply.

Abstract translation: 一种电源开关电路，包括小信号变压器和低功率振荡器，用于在将电源开关与电源的主电源隔离的同时检测电力开关。 当电源开关关闭或者否则按下关闭电源时，振荡器对电容器充电。 耦合到振荡器和电容器的感测和控制电路接地电源的重要信号，保持电源关闭。 在一个实施例中，当开关导通时，它使信号变压器短路振荡器，使得电容器放电，并且感测和控制电路释放重要信号。 在另一个实施例中，电源开关瞬间禁用振荡器并放电电容器，使得感测和控制电路切换触发器电路以接通电源。

公开(公告)号：US5491788A

公开(公告)日：1996-02-13

申请号：US119424

申请日：1993-09-10

Applicant: Darren J. Cepulis ,  Louis R. Gagliardi

Inventor： Darren J. Cepulis ,  Louis R. Gagliardi

IPC: G06F11/14 ,  G06F11/20 ,  G06F11/22 ,  G06F11/00

CPC classification number: G06F11/2041 ,  G06F11/1417 ,  G06F11/2097 ,  G06F11/22

Abstract: A multiprocessor computer system handles the failure of one or more of its processors without totally disabling the system. On power up, all of the CPUs are deactivated except for a CPU in a first physical slot. The power on self test routines review a log of errors and determine if certain critical errors have previously occurred. If so, the CPU in the first physical slot halts operation entirely. If the CPU in the first physical slot is not functioning properly or is halted, the hardware then awakens a CPU in a second physical slot, designates it as the first logical CPU, and the CPU then performs similar diagnostic checks. If it fails, the hardware again tries a third physical CPU and so on. When one CPU passes the initial error review, it proceeds with initialization of the computer system and performs further self testing. If it functions properly, it is designated as the first logical CPU, and retains its designation until the power is cycled. This first logical CPU then awakens the remaining CPUs and boots the rest of the system. If it fails this later self testing by having certain critical errors occur, the logical CPU 0 designation is transferred to another active CPU and the old CPU is halted. The new CPU commences operation effectively where the old CPU halted, so that system initialization is continued not restarted. The power on self test routines then further test the CPU in the first physical slot. Thus, if at least one CPU is operational, the computer system boots and operates.

Abstract translation: 多处理器计算机系统处理一个或多个处理器的故障，而不完全禁用系统。 上电时，除了第一个物理插槽中的CPU之外，所有CPU都将被禁用。 上电自检程序检查错误日志，并确定是否发生了某些严重错误。 如果是这样，第一个物理插槽中的CPU完全停止运行。 如果第一个物理插槽中的CPU运行不正常或停止运行，硬件将唤醒第二个物理插槽中的CPU，将其指定为第一个逻辑CPU，然后CPU执行类似的诊断检查。 如果它失败，硬件再次尝试第三个物理CPU等等。 当一个CPU通过初始错误检查时，它继续进行计算机系统的初始化，并进行进一步的自我测试。 如果它正常工作，它被指定为第一个逻辑CPU，并保持其指定，直到电源循环。 然后，第一个逻辑CPU唤醒剩余的CPU并启动系统的其余部分。 如果通过发生某些严重错误发生后期自检，则将逻辑CPU 0指定传送到另一个活动CPU，并且旧CPU停止。 新CPU在旧CPU停止的情况下开始有效运行，从而不会重新启动系统初始化。 上电自检程序然后进一步测试第一个物理插槽中的CPU。 因此，如果至少有一个CPU正在运行，则计算机系统启动并运行。

公开(公告)号：US5469320A

公开(公告)日：1995-11-21

申请号：US145484

申请日：1993-10-29

Applicant: Richard E. Walker ,  Hai N. Nguyen

Inventor： Richard E. Walker ,  Hai N. Nguyen

IPC: G05D23/24 ,  G06F1/20 ,  H02H3/00

CPC classification number: G06F1/20 ,  G05D23/1906 ,  G05D23/24

Abstract: An efficient fan drive circuit to drive a variable fan used in a power supply of a personal computer system. The fan drive circuit uses a diode to establish the minimum fan speed during operation in the normal temperature range. The bleeder resistor normally coupled between the fan and a negative output voltage is removed and replaced with a current source. The current source also serves to shut down the power supply if the fan is not operating properly or is not installed. A shut down circuit remains to shut down the power supply when excessive temperature occurs, or when the current source detects that the fan is malfunctioning or not installed.

Abstract translation: 一种高效的风扇驱动电路，用于驱动用于个人计算机系统的电源中的可变风扇。 风扇驱动电路使用二极管在正常温度范围内运行时建立最小风扇转速。 通常耦合在风扇和负输出电压之间的泄放电阻器被去除并用电流源代替。 如果风扇运行不正常或未安装，电流源也用于关闭电源。 当发生温度过高或当电源检测到风扇发生故障或未安装时，仍然有一个关闭电路关闭电源。

公开(公告)号：US5463761A

公开(公告)日：1995-10-31

申请号：US955500

申请日：1992-10-02

Applicant: Paul R. Culley

Inventor： Paul R. Culley

IPC: G06F1/14 ,  G06F1/00

CPC classification number: G06F1/14

Abstract: A computer system provides a 48-bit timer having 120 ns resolution and possessing a rollover period in excess of one year. The preferred embodiment includes two system data buffers (SDBs), each of which includes a full 48-bit timer. The timers are synchronized, and the output of each timer is provided to the host bus in alternating pairs of bits, so that half of the data bits are provided by the first SDB and half of the timer bits are provided by the second SDB. The timer may be read either as a 48-bit timer or a 32-bit timer.

Abstract translation: 计算机系统提供了一个具有120ns分辨率并具有超过一年的翻转周期的48位定时器。 优选实施例包括两个系统数据缓冲器（SDB），每个系统数据缓冲器包括一个完整的48位定时器。 定时器被同步，并且每个定时器的输出以交替的位对提供给主机总线，使得一半的数据位由第一SDB提供，一半的定时器位由第二SDB提供。 定时器可以被读取为48位定时器或32位定时器。