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公开(公告)号：US10418584B2
公开(公告)日：2019-09-17
申请号：US15277204
申请日：2016-09-27
Inventor： Liang Zhang , Fuyi Cui , Shanshan Bao , Ang Xiao
Abstract: A sealing method of display panel, comprising: forming closed inner sealant layer in a sealing region of a first substrate; forming outer sealant layer which encloses the inner sealant layer, in which a communicating region is provided, the communicating region is configured to communicate a region between the inner sealant layer and the outer sealant layer and a region outside the outer sealant layer; affixing a second substrate to the first substrate in position to form a motherboard; and sealing the communicating region after cutting out the display panel from the motherboard. A display panel and a display device are also disclosed.
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152.发明授权公开(公告)号：US10403209B2
公开(公告)日：2019-09-03
申请号：US15244830
申请日：2016-08-23
Inventor： Jun Wang , Xinxin Jin , Yi Qu , Yi Zhang , Tianyi Cheng
IPC: G09G3/3266 , G09G3/3291 , G09G3/3258 , H01L27/32 , H01L51/00 , G09G3/3233
Abstract: An array substrate, an electrical aging method, a display device and a manufacturing method thereof. The array substrate includes: pixel circuits disposed in a display area, where each of the pixel circuits is disposed in a corresponding pixel region of the display area; a scanning drive circuit disposed outside the display area; a plurality of scanning-line groups for connecting the pixel circuits to the scanning drive circuit; a voltage input interface disposed outside the display area; and a wire group for connecting the plurality of scanning-line groups to the voltage input interface. An insulating layer is disposed between the wire group and the scanning drive circuit.
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公开(公告)号：US10395597B2
公开(公告)日：2019-08-27
申请号：US15864461
申请日：2018-01-08
Inventor： Hualing Yang , Lina Liu
IPC: G09G3/3258
Abstract: A method for adjusting a gamma voltage of a curved display panel includes following steps. A first gamma voltage is used as a gamma voltage of a planar display region of a curved display panel in a situation that the planar display region of the curved display panel is horizontally placed and in a white balance state. A curved display region of the curved display panel is divided into a plurality of sub-regions according to a bending degree of the curved display region of the curved display panel. A plurality of inclined angles are determined. A plurality of second gamma voltages are determined in a one-to-one correspondence with the plurality of inclined angles in a situation that the planar display region of the curved display panel is tilted at the plurality of inclined angles and in the white balance state.
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154.发明授权公开(公告)号：US10386873B2
公开(公告)日：2019-08-20
申请号：US15508315
申请日：2016-09-07
Inventor： Boya Zhang , Zhaohui Meng , Chenggeng Zhang , Lintao Zhang
IPC: G09G3/3225 , G05F1/46 , G05F1/10 , G09G3/3208
Abstract: Provided are a power supply voltage control circuit and a method thereof, a driver integrated circuit, and a display device. The power supply voltage control circuit comprises: a voltage detection unit (11) configured to detect a power supply voltage (ELVDD, ELVSS) received by the display panel (72) from a power supply circuit (73); a comparison unit (12) configured to obtain a voltage difference between the power supply voltage (ELVDD, ELVSS) and a reference voltage (VF1,VF2) through comparison; and a power supply voltage control unit (13) configured to transmit a power supply voltage control signal to the power supply circuit (73) according to the voltage difference and the reference voltage (VF1,VF2), so that the power supply circuit (73) outputs a corresponding power supply voltage to the display panel (72), so as to compensate for the voltage drop loss during voltage transmission, optimize display effect of the product, reduce effectively the voltage drop loss from the output terminal of the power supply circuit to the display panel side can be, and ensure consistency of the voltages inputted into the display panel.
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155.发明申请公开(公告)号：US20190244824A1
公开(公告)日：2019-08-08
申请号：US16154902
申请日：2018-10-09
Inventor： Haifeng XU , Dawei SHI , Liman PENG , Wentao WANG , Lu YANG , Lei YAO , Jinfeng WANG , Lei YAN , Jinjin XUE , Lin HOU , Fang YAN , Xiaowen SI , Zhijin MAN , Yaoda HOU , Yi LI , Lizhen ZHAO , Lei WANG
CPC classification number: H01L21/3003 , H01L27/1255 , H01L27/1262 , H01L27/1288 , H01L27/3265
Abstract: The present disclosure relates to an array substrate, a method for fabricating the same, a display panel, and a method for fabricating the same. The array substrate includes a substrate, an active layer on the substrate, a first insulating layer on the active layer, a gate electrode and a first electrode on the first insulating layer, wherein a projection of the first electrode on the substrate and a projection of the active layer on the substrate do not overlap, a third insulating layer on the first electrode, a projection of the third insulating layer on the substrate does not overlap with a projection of the active layer on the substrate, a second electrode on the third insulating layer, and a second insulating layer on the gate electrode and the second electrode.
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Patent Agency Ranking
公开(公告)号：US20190237709A1
公开(公告)日：2019-08-01
申请号：US16123296
申请日：2018-09-06
Inventor： Kening Zheng
CPC classification number: H01L51/56 , C09K11/06 , H01L51/001 , H01L51/502 , H01L51/5056 , H01L51/5072 , H01L51/5092 , H01L51/5096 , H01L51/5206 , H01L51/5221 , H01L51/5275
Abstract: An electroluminescent device, a method of manufacturing the electroluminescent device and a display panel are provided. The electroluminescent device includes a first electrode; a second electrode; a light emitting layer between the first electrode and the second electrode; and a light extraction layer on a side of the second electrode facing away from the light emitting layer. The light extraction layer includes a photoresponsive material such that an optical property of the light extraction layer is variable.
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公开(公告)号：US20190233937A1
公开(公告)日：2019-08-01
申请号：US16215829
申请日：2018-12-11
Inventor： Liwei GUAN
Abstract: A loading jig and an evaporator are provided. The loading jig includes a body and at least one elastic membrane. The body has a plate-like structure and is sandwiched between the bearing platform and the plurality of clamping blocks. Said at least one elastic membrane is respectively disposed between at least one clamping block and a bottom of the body. The elastic membrane is externally connected to a signal converter. The pressure applied by the clamping block may be measured through the elastic membrane when the clamping block is pressed against the bottom of the body, and then the measured pressure signal is transmitted to the signal converter to be converted into a pressure value.
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公开(公告)号：US10355097B2
公开(公告)日：2019-07-16
申请号：US15710133
申请日：2017-09-20
Inventor： Lu Yang , Wentao Wang , Xiaowen Si , Haifeng Xu , Jinfeng Wang , Lei Yan , Lei Yao , Feng Li
IPC: H01L29/423 , H01L27/12 , H01L29/66 , H01L29/786
Abstract: The present disclosure provides a thin film transistor (TFT), an array substrate, a display panel and a display device. The TFT includes a gate electrode, a gate insulating layer, a source electrode, a drain electrode and an active layer arranged on a base substrate, wherein there is a plurality of overlapping regions separated from each other where a projection of the gate electrode on the base substrate and a projection of the active layer on the base substrate overlap each other.
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公开(公告)号：US20190204970A1
公开(公告)日：2019-07-04
申请号：US16170330
申请日：2018-10-25
Inventor： Peirong Huo , Zhiqiang Wang , Jingyi Xu , Fang Yan
CPC classification number: G06F3/0412 , G06F3/0416 , G06F3/044
Abstract: An array substrate, a touch display panel and a display device are provided. The array substrate includes: a common electrode and a conductive pattern which are on a base substrate, the common electrode includes a plurality of common electrode blocks arranged in an array; the conductive pattern includes a plurality of groups of connecting wires; each group of connecting wires is configured to electrically connect a touch driving circuit with one common electrode block; each group of connecting wires includes at least one conducting wire; each conducting wire includes a first conductive wire segment located in a lead region and a second conductive wire segment located in a connecting region and configured to connect the first conductive wire segment with the common electrode block; for each common electrode block group, the length of the second conductive wire segment is negatively correlated with the length of the first conductive wire segment.
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公开(公告)号：US20190185984A1
公开(公告)日：2019-06-20
申请号：US16054076
申请日：2018-08-03
Inventor： Chunchieh Huang , Shouhua Lv
CPC classification number: C23C14/042 , C23C14/12 , C23C14/22 , H01L51/0011 , H01L51/56
Abstract: The disclosure relates to the field of vapor-plating technologies, and discloses a mask strip, a mask, and a vapor-plating device to thereby improve the quality of vapor plating. The mask strip includes solder holes for soldering on a upper surface of a frame of a mask, and a first groove which is on the sides of the solder holes away from the upper surface of the frame, and communicates with the solder holes.
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