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公开(公告)号：US20230058149A1
公开(公告)日：2023-02-23
申请号：US17969736
申请日：2022-10-20
发明人： Huazi ZHANG , Jiajie TONG , Xianbin WANG , Shengchen DAI , Rong LI , Jun WANG
IPC分类号： H03M13/11
摘要： An encoding method and apparatus, a decoding method and apparatus, and a device are provided. The encoding method includes obtaining K to-be-encoded bits (S301), where K is a positive integer; determining a first generator matrix, where the first generator matrix includes at least two sub-blocks distributed based on a preset position relationship, and the sub-block includes a plurality of first generator matrix cores (S302); generating a second generator matrix based on the first generator matrix, where the second generator matrix includes T sub-blocks, and a position relationship between two adjacent sub-blocks of the T sub-blocks is determined based on the preset position relationship (S303), where T is a positive integer; and polar encoding the K to-be-encoded bits based on the second generator matrix (S304), to obtain encoded bits. This reduces encoding/decoding complexity.
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公开(公告)号：US20230049851A1
公开(公告)日：2023-02-16
申请号：US17874212
申请日：2022-07-26
申请人： Intel Corporation
发明人： Kjersten E. CRISS
摘要： An apparatus is described. The apparatus includes a memory chip. The memory chip has an error correction code (ECC) encoder logic circuit and an ECC decoder logic circuit. The ECC decoder logic circuit is to place an additional one or more errors that result from incorrect error correction applied to a read code word into a same block of multiple blocks of the read code word's raw data bit portion where original errors in the read code word existed before the read code word was decoded by the ECC decoder logic circuit.
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公开(公告)号：US11582594B2
公开(公告)日：2023-02-14
申请号：US17068345
申请日：2020-10-12
摘要： Methods and systems for managing decoding of control channel on a multi-SIM UE. A method includes receiving, by the UE, the plurality of control channels from at least one Base Station (BS), the plurality of control channels corresponding to a plurality of Subscriber Identity Modules (SIMs), selecting, by the UE, a respective decoder for each of the plurality of SIMs, and decoding, by the UE, each respective control channel among the plurality of control channels using the respective decoder for a respective SIM among the plurality of SIMs, the respective SIM corresponding to the respective control channel.
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公开(公告)号：US11581904B2
公开(公告)日：2023-02-14
申请号：US17024517
申请日：2020-09-17
发明人： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for quadrature phase shift keying (QPSK) modulation.
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公开(公告)号：US20230041662A1
公开(公告)日：2023-02-09
申请号：US17959570
申请日：2022-10-04
发明人： Mihail PETROV
摘要： A bit interleaving method involves applying a bit permutation process to a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N/M folding sections, each of the constellation words being associated with one of the F×N/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word
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公开(公告)号：US20230037996A1
公开(公告)日：2023-02-09
申请号：US17718422
申请日：2022-04-12
发明人： Sungrae Kim , Myungkyu Lee , Kijun Lee , Sunghye Cho
摘要： An operating method of a memory device includes storing position information regarding a codeword including an erasure and erasure information including position information regarding the erasure in a memory region, loading the position information regarding the codeword to a row decoder and a column decoder, determining whether a read address corresponding to a read instruction is identical to the position information regarding the codeword including the erasure, in response to the read instruction from a host, transmitting the position information of the erasure to an error correction code (ECC) decoder, when the read address is identical to the position information regarding the codeword including the erasure, and correcting, by the ECC decoder, an error in a codeword received from a memory cell array using the position information regarding the erasure.
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公开(公告)号：US20230036512A1
公开(公告)日：2023-02-02
申请号：US17961410
申请日：2022-10-06
申请人： Intel Corporation
IPC分类号： H03M13/11
摘要： A low-density parity-check (LDPC) decoder performs check node computations as N different segments of the check nodes which have connections only to a codeword segment of length C/N bits as well as check nodes that have connections across the entire codeword of length C. The decoder can include a controller or other compute hardware to decode the codeword, including to perform computations for separate segments of C/N bits of the codeword. The system can perform computations including adjustment of the decode computations based on an expected error rate for selected segments of the codeword.
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公开(公告)号：US20230017120A1
公开(公告)日：2023-01-19
申请号：US17952533
申请日：2022-09-26
申请人： Ciena Corporation
摘要： A transmitter generates an encoded vector by encoding a data vector, the encoded vector representing payload information and parity information. The encoding is mathematically equivalent to calculating three or more forward error correction (FEC) codewords from the data vector and then calculating the encoded vector from the codewords, at least one codeword being calculated from at least one recursion of a mathematical operation, and at least one codeword comprising more than 6 terms. The transmitter transmits a signal representing the encoded vector over a communication channel. A receiver determines a vector estimate from the signal and recovers the data vector from the vector estimate by sequentially decoding the codewords, wherein at least one codeword that is decoded earlier in the decoding enhances an estimate of at least one codeword that is decoded later in the decoding.
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公开(公告)号：US11556418B2
公开(公告)日：2023-01-17
申请号：US17060768
申请日：2020-10-01
发明人： Sung-Ik Park , Sun-Hyoung Kwon , Bo-Mi Lim , Jae-Young Lee , Heung-Mook Kim , Nam-Ho Hur
摘要： A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 10/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 256-symbol mapping.
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公开(公告)号：US11556417B1
公开(公告)日：2023-01-17
申请号：US17559995
申请日：2021-12-22
摘要： A memory device to use added known data as part of data written to memory cells with redundant data generated according to an Error Correction Code (ECC). The code rate of the ECC may limit its capability to recover from excessive errors in the stored data. To reduce the errors, the added data retrieved from the memory cells can be corrected without using the ECC. Subsequently, remaining errors can be corrected via the ECC. Optionally, the added data can be configured to be the same as the data represented by an erased state of a subset of the memory cells such that when the subset is used to store the added data, the subset remains in the erased state to reduce wearing. Different subsets can be used to store added data for different write operations to distribute the benefit of reduced wearing.
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