公开(公告)号：US5311085A

公开(公告)日：1994-05-10

申请号：US867594

申请日：1992-04-13

Applicant: Marcellinus J. M. Pelgrom ,  Antonia C. Van Rens

Inventor： Marcellinus J. M. Pelgrom ,  Antonia C. Van Rens

IPC: H03K5/08 ,  G11C27/02 ,  H03K5/24

CPC classification number: H03K5/249 ,  G11C27/026

Abstract: A clocked comparator circuit comprises an input stage and a sample-and-hold circuit and an amplifier-latch circuit coupled to the output of the input stage. The sample-and-hold circuit provides an accurate offset-voltage compensation and the amplifier-latch circuit provides a high operating speed by means of a switchable current source (S6, T11). Switches are provided so that the amplifier-latch circuit constitutes a differential load having a high positive impedance during a first state of a clock signal, a low positive impedance during a next state of the clock signal, and a negative impedance during a following state of the clock signal.

Abstract translation: 时钟比较器电路包括输入级和采样保持电路以及耦合到输入级的输出的放大器 - 锁存电路。 采样保持电路提供精确的失调电压补偿，放大器锁存电路通过可切换电流源（S6，T11）提供高工作速度。 提供开关，使得放大器锁存电路构成在时钟信号的第一状态期间具有高正阻抗的差分负载，在时钟信号的下一状态期间为低正阻抗，以及在后续状态期间为负阻抗 时钟信号。

公开(公告)号：US5262685A

公开(公告)日：1993-11-16

申请号：US778350

申请日：1991-10-16

Applicant: Michael J. Demler ,  Kevin J. McCall

Inventor： Michael J. Demler ,  Kevin J. McCall

IPC: G11C27/02 ,  H03K5/24

CPC classification number: G11C27/026 ,  H03K5/249

Abstract: Auto-zeroing clocking signals, a first auto-zeroing clocking signal of comparatively-low frequency and duty cycle and a second auto-zeroing clocking signal of the same comparatively-low frequency but complementary and comparatively-high duty cycle, and a sampling clocking signal of comparatively-high frequency respectively initiate auto-zeroing of a circuit element subject to output offset error and data sampling of an A.C. input signal to a latch. The sampling of the A.C. input signal to the latch occurs at the comparatively-high frequency of the clocking signal during the "on" time of the comparatively-high duty cycle second auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide higher speed sampling than heretofore possible. The auto-zeroing of the circuit element subject to input offset error occurs during the "on" time of the comparatively-low duty cycle first auto-zeroing clocking signal of comparatively-low frequency enabling thereby to provide lower power sampling than heretofore possible. Typically, the circuit element is either an analog comparator or an operational amplifier, and the sampling circuit of the invention has exemplary utility in analog-to-digital (A/D) conversion.

Abstract translation: 自动归零时钟信号，具有相对较低频率和占空比的第一自动归零时钟信号和具有相同较低频率但互补且相对较高占空比的相同低自适应时钟信号，以及采样时钟信号 相对高的频率分别启动电路元件的自动归零，该电路元件受到输出偏移误差的影响，并将AC输入信号的数据采样到锁存器。 在较低频率的比较高占空比的第二自动归零时钟信号的“接通”时间内，对锁存器的AC输入信号的采样发生在时钟信号的较高频率处，从而能够提供更高的 速度采样比以前可能。 受到输入偏移误差的电路元件的自动归零发生在相对低频率的相对低的占空比第一自动归零时钟信号的“导通”时间，从而能够提供比以前更低的功率采样。 通常，电路元件是模拟比较器或运算放大器，并且本发明的采样电路在模数（A / D）转换中具有示例性的用途。

公开(公告)号：US5239181A

公开(公告)日：1993-08-24

申请号：US636808

申请日：1990-12-31

Applicant: Chen-Kuo Sun ,  Chao C. Wu ,  Ching T. Chang ,  Paul K. Lai Yu ,  William H. McKnight

Inventor： Chen-Kuo Sun ,  Chao C. Wu ,  Ching T. Chang ,  Paul K. Lai Yu ,  William H. McKnight

IPC: G11C27/02 ,  H03K17/78

CPC classification number: G11C27/026 ,  H03K17/78

Abstract: A novel bridge type optoelectronic (OE) sample and hold circuit based upon current steering demonstrates a clear superiority in performance with respect to a direct OE sample and hold circuit. The bridge type OE sample and hold circuit permits a high-speed signal to be sampled with high accuracy to offer high charging capability, commanding signal isolation, reduced time jitter and reduced holding charge leakage which are distinct advantages over conventional electronic sample and hold circuits.

Abstract translation: 基于电流转向的新型桥式光电（OE）采样和保持电路在直接OE采样保持电路方面表现出明显的性能优势。 桥式OE采样保持电路允许以高精度对高速信号进行采样，以提供高充电能力，指令信号隔离，减少时间抖动和降低保持电荷泄漏，这与传统电子采样和保持电路相比是显着的优点。

公开(公告)号：US5185635A

公开(公告)日：1993-02-09

申请号：US737112

申请日：1991-07-29

Applicant: William A. Trent ,  Kevin B. McDonald ,  Florian G. Bell

Inventor： William A. Trent ,  Kevin B. McDonald ,  Florian G. Bell

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: An input signal is sampled by alternately coupling the input signal and a reference level to a sample storage element, whereby the magnitude of the signal stored by the storage element immediately following application of the input signal to the storage element is a function of the input signal magnitude and the magnitude of the signal stored by the storage element immediately preceding coupling of the input signal to the storage element is a function of the reference level.

Abstract translation: 通过将输入信号和参考电平交替地耦合到采样存储元件来对输入信号进行采样，由此将紧随施加输入信号的存储元件存储的信号的幅度作为输入信号的函数 幅度和由紧接在输入信号耦合到存储元件之前的存储元件存储的信号的幅度是参考电平的函数。

公开(公告)号：US5164915A

公开(公告)日：1992-11-17

申请号：US644239

申请日：1991-01-22

Applicant: Trevor Blyth

Inventor： Trevor Blyth

IPC: G10L13/04 ,  G11C7/16 ,  G11C11/56 ,  G11C27/00 ,  G11C27/02 ,  G11C27/04

CPC classification number: G11C7/16 ,  G11C11/5621 ,  G11C27/005 ,  G11C27/026 ,  G11C2207/16

Abstract: Cascading analog record/playback devices allowing the recording and the playback duration of individual devices to be extended by connecting together multiple devices of the same type. Each such device contains both writing and reading circuits as well as memory circuits. The memory is embedded inside the device and does not have direct access to the outside of the device. All control functions relating to the selection of particular devices is done by the devices themselves without external intervention or assistance. A single input circuit and a single output circuit is used by all devices. In the case of a voice record and playback system, all devices use a single microphone and single loudspeaker.

Abstract translation: 通过将多个相同类型的设备连接在一起，可以扩展单个设备的记录和播放持续时间的级联模拟记录/播放设备。 每个这样的设备都包含写入和读取电路以及存储器电路。 内存嵌入设备内部，不能直接访问设备的外部。 与特定设备的选择相关的所有控制功能都由设备本身完成，无需外部干预或协助。 所有设备都使用单个输入电路和单个输出电路。 在语音记录和播放系统的情况下，所有设备都使用单个麦克风和单个扬声器。

公开(公告)号：US5162670A

公开(公告)日：1992-11-10

申请号：US636427

申请日：1990-12-28

Applicant: Tetsuro Itakura ,  Takeshi Shima

Inventor： Tetsuro Itakura ,  Takeshi Shima

IPC: G09G3/36 ,  G11C27/02

CPC classification number: G11C27/026 ,  G11C27/024 ,  G09G2310/0289 ,  G09G3/3688

Abstract: A sample-and-hold circuit includes a first switch element which is opened or closed in accordance with a first control signal so as to selectively connect an input signal terminal for receiving an input signal to an internal terminal, a non-linear element for connecting the internal terminal to an output terminal, a potential holding circuit connected between the output terminal and ground, and a second switch element or a current source circuit which is controlled by a second control signal so as to selectively connect the output terminal to ground.

公开(公告)号：US5148055A

公开(公告)日：1992-09-15

申请号：US794143

申请日：1991-11-19

Applicant: Kazunori Nohara

Inventor： Kazunori Nohara

IPC: G11C27/02 ,  H04N5/18 ,  H04N9/72

CPC classification number: H04N9/72 ,  G11C27/024 ,  G11C27/026 ,  H04N5/185

Abstract: A holding circuit used in a pedestal level clamp circuit of a color television receiver. By using base current of a transistor as charging current of a capacitor, a large time constant is obtained. Also, in case the voltage lower than the reference voltage is held, base current of the transistor is used as discharging current to discharge slowly. Furthermore, though a charging transistor of the capacitor must be a PNP type and a discharging transistor must be an NPN type, it is designed not to be influenced by the difference in current amplification factors of the two types.

Abstract translation: 一种用于彩色电视接收机的基座电平钳位电路的保持电路。 通过使用晶体管的基极电流作为电容器的充电电流，可获得大的时间常数。 另外，在保持低于参考电压的电压的情况下，晶体管的基极电流被用作放电电流以缓慢放电。 此外，尽管电容器的充电晶体管必须是PNP型，而放电晶体管必须是NPN型，但不受这两种类型的电流放大系数的差异的影响。

公开(公告)号：US5142284A

公开(公告)日：1992-08-25

申请号：US814303

申请日：1991-12-23

Applicant: William A. Trent ,  Kevin B. McDonald ,  Florian G. Bell ,  Richard I. Lane ,  Glenn Bateman ,  Michael S. Overton

Inventor： William A. Trent ,  Kevin B. McDonald ,  Florian G. Bell ,  Richard I. Lane ,  Glenn Bateman ,  Michael S. Overton

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: An input signal is sampled by alternately coupling the input signal and a reference level to a sample storage element, whereby the magnitude of the signal stored by the storage element immediately following application of the input signal to the storage element is a function of the input signal magnitude and the magnitude of the signal stored by the storage element immediately preceding coupling of the input signal to the storage element is a function of the reference level.

Abstract translation: 通过将输入信号和参考电平交替地耦合到采样存储元件来对输入信号进行采样，由此将紧随施加输入信号的存储元件所存储的信号的幅度作为输入信号的函数 幅度和由紧接在输入信号耦合到存储元件之前的存储元件存储的信号的幅度是参考电平的函数。

公开(公告)号：US5047666A

公开(公告)日：1991-09-10

申请号：US513910

申请日：1990-04-24

Applicant: Berthold Astegher ,  Alexander Lechner ,  Hermann Jessner

Inventor： Berthold Astegher ,  Alexander Lechner ,  Hermann Jessner

IPC: G11C27/02 ,  H03F1/30

CPC classification number: H03F1/303 ,  G11C27/026

Abstract: A circuit configuration includes a symmetrically constructed sample and hold amplifier. A first switchable level shifter has an input in the form of a first signal input terminal for receiving a given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. A second switchable level shifter has an input in the form of a second signal input terminal for receiving a signal complementary to the given signal, and an output being connected to the sample and hold amplifier for supplying a differential output signal. The input and output signals of each of the switchable level shifters having a different constant direct voltage difference as a function of the switching state of the level shifters.

Abstract translation: 电路配置包括对称构造的采样和保持放大器。 第一可切换电平移位器具有用于接收给定信号的第一信号输入端子形式的输入，以及连接到采样和保持放大器以提供差分输出信号的输出。 第二可切换电平移位器具有用于接收与给定信号互补的信号的第二信号输入端子形式的输入，以及连接到采样和保持放大器以提供差分输出信号的输出。 每个可切换电平移位器的输入和输出信号具有作为电平移位器的开关状态的函数的不同的恒定直流电压差。

公开(公告)号：US5017924A

公开(公告)日：1991-05-21

申请号：US514888

申请日：1990-04-26

Applicant: Christian Guiberteau ,  Michele Le Paih ,  Stephane Ruggeri

Inventor： Christian Guiberteau ,  Michele Le Paih ,  Stephane Ruggeri

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: Disclosed is a sample-and-hold unit more especially designed to work at microwave frequencies (>1 GHz). In order to increase the sampling frequency, the disclosed circuit has at least two identical parallel channels. Each channel has a first follower switch (9) a capacitor (11) and a second holding switch (15). The channels are controlled by a single clock, the complementary or phase-shifted signals (H, H) of which address the samples sequentially towards the output (8). The disclosed device can be applied to the processing of analog signals.

Abstract translation: 公开了一种采样保持单元，更专门设计用于在微波频率（> 1GHz）下工作。 为了增加采样频率，所公开的电路具有至少两个相同的并行通道。 每个通道具有第一跟随开关（9）电容器（11）和第二保持开关（15）。 通道由单个时钟控制，互补或相移信号（H，＆amp; upbar＆amp; H）依次向输出端（8）寻址采样。 所公开的设备可以应用于模拟信号的处理。