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公开(公告)号：US20180315388A1
公开(公告)日：2018-11-01
申请号：US15565756
申请日：2017-03-29
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Seungwoo Han , Guangliang Shang
IPC: G09G3/36 , H01L27/12 , H01L29/786
CPC classification number: G09G3/3677 , G02F1/13624 , G02F1/1368 , G02F2202/10 , G09G3/20 , G09G3/3225 , G09G3/36 , G09G3/3648 , G09G3/3688 , G09G2300/0404 , G09G2300/0426 , G09G2300/0819 , G09G2310/0205 , G09G2310/021 , G09G2320/043 , G09G2320/045 , H01L27/1225 , H01L27/124 , H01L29/7869
Abstract: The present application discloses an array substrate comprising a plurality of gate lines and a plurality of data lines crossing over each other thereby defining an array of a plurality of sub-pixel areas, each sub-pixel area comprising a pixel electrode and multiple switching transistors having respective gate electrodes coupled to multiple different gate lines, wherein the pixel electrode is configured to be charged by a data signal from a data line only with all the multiple switching transistors being turned on concurrently during a pixel electrode charging period by an effective voltage level applied on the respective multiple different gate lines.
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132.发明申请公开(公告)号：US20180301200A1
公开(公告)日：2018-10-18
申请号：US15520191
申请日：2016-11-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Seungwoo Han , Mingfu Han , Haoliang Zheng , Xing Yao , Hyunsic Choi
CPC classification number: G11C19/28 , G09G3/20 , G09G3/3677 , G09G2310/0286 , G09G2310/06 , G09G2310/08 , G09G2330/06
Abstract: The present application discloses a control circuit for controlling a noise reduction thin film transistor in a shift register unit. The control circuit includes a timer for initiating a timing process when the shift register is turned on, to obtain an operating time of the shift register; a threshold voltage calculator coupled to the timer for calculating a present threshold voltage based on the operating time, a gate voltage of the noise reduction thin film transistor, and an initial threshold voltage of the noise reduction thin film transistor; and a gate voltage controller coupled to the threshold voltage calculator for adjusting the gate voltage of the noise reduction thin film transistor during the noise reduction phase, to control the noise reduction thin film transistor in an ON state during the noise reduction phase.
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公开(公告)号：US10096374B2
公开(公告)日：2018-10-09
申请号：US15539220
申请日：2016-11-01
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Guangliang Shang , Seungwoo Han , Haoliang Zheng , Xing Yao , Mingfu Han , Hyunsic Choi , Yunsik Im , Yinglong Huang , Jungmok Jun , Xue Dong
Abstract: The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.
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134.发明申请公开(公告)号：US20180190180A1
公开(公告)日：2018-07-05
申请号：US15680416
申请日：2017-08-18
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang Shang , Mingfu Han , Haoliang Zheng , Han-Seung- Woo , Im-Yun- Sik , Jing Lv , Yinglong Huang , Jun-Jung- Mok , Xue Dong , Zhichong Wang , Xing Yao , Lijun Yuan , Zhihe Jin
CPC classification number: G09G3/2092 , G09G3/3266 , G09G3/3677 , G09G2300/0809 , G09G2310/0267 , G09G2310/0286 , G09G2310/08 , G09G2320/043 , G09G2330/02 , G11C19/28
Abstract: Embodiments of the present disclosure provide a shift register unit, a driving method thereof, a gate driving circuit, and a display device. The shift register unit comprises an input circuit, a reset circuit, a plurality of output circuits, a plurality of pull-down circuits and a plurality of pull-down control circuits. During a first time period, all of signals output by the plurality of output circuits are valid. During a second time period, at least one of the signals output by the plurality of output circuits is invalid, wherein the second time period comprises a first sub-period and a second sub-period, and the state of at least one of the signals output by the plurality of output circuits during the first sub-period is opposite to the state thereof during the second sub-period. The shift register unit may enable transistors in a pixel circuit to switch between ON and OFF states, so as to extend lifetime of the transistors.
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Patent Agency Ranking
公开(公告)号：US10013946B2
公开(公告)日：2018-07-03
申请号：US15126641
申请日：2015-12-31
Applicant: BOE Technology Group Co., Ltd.
Inventor： Feng Liao , Guangliang Shang , Kuanjun Peng
CPC classification number: G09G3/38 , G09G3/3233 , G09G2300/0819 , G09G2300/0842 , G09G2310/0262 , G09G2320/0233 , G09G2320/029 , G09G2320/043 , G09G2320/045 , G09G2360/16
Abstract: The present disclosure discloses a pixel driving circuit and a driving method thereof, a display panel and a display apparatus, and relates to a field of display technology, in order to solve a problem of the conventional light-emitting element being unable to emit light within a short period of time during which no current flows through the light-emitting element so that the conventional display apparatus has a bad display effect. The pixel driving circuit comprises a first input module, a second input module, a charging module for charging a storage module, the storage module for storing quantity of electricity between a compensation module and a light-emitting element, a power supply control module, the compensation module, a driving module for providing the light-emitting element with a signal of a DC power supply signal terminal and a light-emitting element. The pixel driving circuit provided by the present disclosure is applied in the display apparatus.
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公开(公告)号：US10002675B2
公开(公告)日：2018-06-19
申请号：US15504119
申请日：2016-08-12
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Haoliang Zheng , Seungwoo Han , Xing Yao , Hyunsic Choi , Guangliang Shang , Mingfu Han , Yunsik Im , Jungmok Jun , Xue Dong
CPC classification number: G11C19/28 , G09G3/20 , G09G3/3677 , G09G3/3688 , G09G2310/0267 , G09G2310/0286 , G11C19/184 , H01L27/1222 , H01L27/124 , H01L27/1251
Abstract: The present application discloses a method of driving a gate driving circuit in an operation cycle divided into a first sub-cycle and a second sub-cycle, including providing a gate driving circuit having a first plurality of shift register units with a second plurality of shift register units, the first plurality of shift register units being configured so that each odd/even numbered shift register unit includes a first bias-control terminal to receive a first/second bias signal CLK1/CLK2, a second bias-control terminal to receive a second/first bias signal CLK2/CLK1, and a first control level terminal provided with a first control voltage VC1, the second plurality of shift register units being configured so that each odd/even numbered shift register unit includes a third bias-control terminal to receive a third/fourth bias signal CLK3/CLK4, a fourth bias-control terminal to receive a fourth/third bias signal CLK4/CLK3, and a second control level terminal provided with a second control voltage VC2; configuring the first bias signal CLK1 and the second bias signal CLK2 as first pair of clock signals at respective turn-on level and turn-off level with inverted phase in the first sub-cycle; setting the first control voltage VC1 to a turn-off level so that the first plurality of shift register units is controlled along with the first pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the first sub-cycle; setting both the third bias signal CLK3 and the fourth bias signal CLK4 to a turn-off level and the second control voltage VC2 to turn-on level during the first sub-cycle; configuring the third bias signal CLK3 and the fourth bias signal CLK4 as second pair of clock signals at respective turn-on level and turn-off level with inverted phase in the second sub-cycle; setting the second control voltage VC2 to a turn-off level so that the second plurality of shift register units are controlled along with the second pair of clock signals to respectively output corresponding gate driving output signals in an output phase within the second sub-cycle; and setting the first bias signal CLK1 and the second bias signal CLK2 to a turn-off level and the second control voltage VC1 to a turn-on level during the second sub-cycle.
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公开(公告)号：US20160210915A1
公开(公告)日：2016-07-21
申请号：US14917335
申请日：2015-08-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Yanfeng Wang , Guangliang Shang , Xiaoling Xu
IPC: G09G3/36
Abstract: A pixel circuit and driving method thereof and display apparatus are disclosed. The pixel circuit comprises: a selection circuit (P1), whose input terminal is connected to a selection signal terminal, a high level signal terminal and a low level signal terminal, configured to control charging or discharging of a pixel capacitor according to a digital signal input by the selection signal terminal; a charging/discharging circuit (P2), whose input terminal is connected to an output terminal of the selection circuit and a same row gate line signal terminal corresponding to the pixel capacitor and output terminal is connected to the pixel capacitor, configured to charge or discharge the pixel capacitor under the control of the selection circuit; and a pre-charging circuit (P3), whose input terminal is connected to a previous row gate line signal terminal corresponding to the pixel capacitor and output terminal is connected to the pixel capacitor, configured to provide a reference voltage. This pixel circuit saves the digital-analogy conversion circuit and the analogy circuit part in the driving IC.
Abstract translation: 公开了像素电路及其驱动方法和显示装置。 像素电路包括：选择电路（P1），其输入端子连接到选择信号端子，高电平信号端子和低电平信号端子，被配置为根据数字信号控制像素电容器的充电或放电 由选择信号端输入; 其输入端子连接到选择电路的输出端子和对应于像素电容器和输出端子的相同行栅极线信号端子的充电/放电电路（P2）连接到像素电容器，被配置为充电或放电 在选择电路的控制下的像素电容; 和预充电电路（P3），其输入端子连接到与像素电容器对应的前一行栅极线信号端子，并且输出端子连接到像素电容器，被配置为提供参考电压。 该像素电路将数模转换电路和类比电路部分保存在驱动IC中。
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公开(公告)号：US09373414B2
公开(公告)日：2016-06-21
申请号：US14162054
申请日：2014-01-23
Inventor： Guangliang Shang
CPC classification number: G11C19/28 , G09G3/3677 , G09G2310/0286 , G11C19/184
Abstract: A shift register unit and a gate drive device for a liquid crystal display are disclosed. Both gate and drain of the tenth thin film transistor are connected to the source of the fifth thin film transistor, a source thereof is connected to a low voltage signal input terminal, threshold voltages of the eighth thin film transistor and the ninth thin film transistor are equal to or less than threshold voltage of the tenth thin film transistor. The shift register unit and the gate drive device for liquid crystal display provided in the present invention, could enable the thin film transistor used to suppress the noise in the shift register unit to maintain turning on, therefore it guarantees the reliability of the shift register unit.
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139.发明申请公开(公告)号：US20140160382A1
公开(公告)日：2014-06-12
申请号：US14103234
申请日：2013-12-11
Applicant: BOE Technology Group Co., Ltd.
Inventor： Guangliang Shang , Lilei Zhang
IPC: G02F1/1335
CPC classification number: G09G3/3648 , G09G3/003 , G09G3/3607 , G09G3/3614 , G09G2300/0452
Abstract: The present invention provides a method for driving a liquid crystal display panel and a liquid crystal display so that the power consumption for driving a 3D liquid crystal display panel can be reduced. The method includes steps of: determining that it is needed to input data to the black matrix sub-pixels when displaying a 3D image; and inputting a control signal to a 3D black screen data control module, the 3D black screen data control module, based on the received control signal, makes two data lines which are connected therewith and are of opposite polarities be electrically conducted.
Abstract translation: 本发明提供一种用于驱动液晶显示面板和液晶显示器的方法，从而可以降低用于驱动3D液晶显示面板的功耗。 该方法包括以下步骤：确定在显示3D图像时需要向黑矩阵子像素输入数据; 并且将控制信号输入到3D黑屏数据控制模块，3D黑屏数据控制模块基于接收到的控制信号，使与之连接并具有相反极性的两条数据线被电导通。
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