公开(公告)号：US20140252297A1

公开(公告)日：2014-09-11

申请号：US13791659

申请日：2013-03-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chih-Yang Chang ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Hsia-Wei Chen ,  Yu-Wen Liao ,  Chin-Chieh Yang

IPC: H01L45/00

CPC classification number: H01L45/1666 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/145 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675 ,  Y10S438/90

Abstract: A method for forming a resistive memory cell within a memory array includes forming a patterned stopping layer on a first metal layer formed on a substrate and forming a bottom electrode into features of the patterned stopping layer. The method further includes forming a resistive memory layer. The resistive memory layer includes a metal oxide layer and a top electrode layer. The method further includes patterning the resistive memory layer so that the top electrode layer acts as a bit line within the memory array and a top electrode of the resistive memory cell.

Abstract translation: 用于在存储器阵列内形成电阻存储单元的方法包括在形成在衬底上的第一金属层上形成图案化的阻挡层，并形成底部电极作为图案化阻挡层的特征。 该方法还包括形成电阻存储层。 电阻性存储层包括金属氧化物层和顶部电极层。 该方法还包括图案化电阻性存储层，使得顶部电极层用作存储器阵列内的位线和电阻存储器单元的顶部电极。

公开(公告)号：US20140203236A1

公开(公告)日：2014-07-24

申请号：US13746187

申请日：2013-01-21

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hsia-Wei Chen ,  Wen-Ting Chu ,  Kuo-Chi Tu ,  Chin-Chieh Yang ,  Chih-Yang Chang ,  Yu-Wen Liao

IPC: H01L45/00

CPC classification number: H01L45/1246 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1266 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1675

Abstract: The present disclosure provides a resistive random access memory (RRAM) cells and methods of making the same. The RRAM cell includes a transistor and an RRAM structure. The RRAM structure includes a bottom electrode having a via portion and a top portion, a resistive material layer on the bottom electrode having a width that is same as a width of the top portion of the bottom electrode; a capping layer over the bottom electrode; a spacer surrounding the capping layer; and, a top electrode on the capping layer having a smaller width than the resistive material layer. The RRAM cell further includes a conductive material connecting the top electrode of the RRAM structure to a metal layer.

Abstract translation: 本公开提供了一种电阻随机存取存储器（RRAM）单元及其制造方法。 RRAM单元包括晶体管和RRAM结构。 RRAM结构包括具有通孔部分和顶部部分的底部电极，底部电极上的电阻材料层具有与底部电极的顶部部分的宽度相同的宽度; 底部电极上的覆盖层; 包围覆盖层的间隔物; 并且所述覆盖层上的顶部电极具有比所述电阻材料层更小的宽度。 RRAM单元还包括将RRAM结构的顶部电极连接到金属层的导电材料。

公开(公告)号：US20140151782A1

公开(公告)日：2014-06-05

申请号：US14176968

申请日：2014-02-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Yong-Shiuan Tsair ,  Wen-Ting Chu ,  Po-Wei Liu ,  Wen-Tuo Huang ,  Yu-Hsiang Yang ,  Chieh-Fei Chiu ,  Yu-Ling Hsu

IPC: H01L21/28 ,  H01L29/423 ,  H01L27/115

CPC classification number: H01L21/28273 ,  H01L27/11517 ,  H01L29/42328 ,  H01L29/7881

Abstract: Methods and apparatus for non-volatile memory cells with increased programming efficiency. An apparatus is disclosed that includes a control gate formed over a portion of a floating gate formed over a semiconductor substrate. The control gate includes a source side sidewall spacer adjacent a source region in the semiconductor substrate and a drain side sidewall spacer, the floating gate having an upper surface portion adjacent the source region that is not covered by the control gate; an inter-poly dielectric over the source side sidewall spacer and the upper surface of the floating gate adjacent the source region; and an erase gate formed over the source region and overlying the inter-poly dielectric, and adjacent the source side sidewall of the control gate, the erase gate overlying at least a portion of the upper surface of the floating gate adjacent the source region. Methods for forming the apparatus are provided.

Abstract translation: 提高编程效率的非易失性存储单元的方法和装置。 公开了一种装置，其包括形成在半导体衬底上形成的浮动栅极的一部分上的控制栅极。 所述控制栅极包括邻近所述半导体衬底中的源极区域的源极侧壁间隔壁和漏极侧壁间隔物，所述浮置栅极具有邻近所述源极区域的未被所述控制栅极覆盖的上表面部分; 在源极侧壁间隔物上的多晶硅电介质和邻近源极区域的浮置栅极的上表面; 以及擦除栅极，形成在源极区域上并且覆盖多晶硅电介质并且邻近控制栅极的源极侧壁，擦除栅极覆盖邻近源极区域的浮置栅极的上表面的至少一部分。 提供了形成装置的方法。