知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

148 records (took 0.026 seconds)

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    111.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20210193668A1

    公开(公告)日：2021-06-24

    申请号：US17194324

    申请日：2021-03-08

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Yu-Hsiang Hung ,  Ming-Te Wei

    IPC: H01L27/108

    Abstract: The present invention provides a semiconductor device, the semiconductor device includes a substrate, at least one bit line is disposed on the substrate, a rounding hard mask is disposed on the bit line, and the rounding hard mask defines a top portion and a bottom portion, and at least one storage node contact plug, located adjacent to the bit line, the storage node contact structure plug includes at least one conductive layer, from a cross-sectional view, the storage node contact plug defines a width X1 and a width X2. The width X1 is aligned with the top portion of the rounding hard mask in a horizontal direction, and the width X2 is aligned with the bottom portion of the rounding hard mask in the horizontal direction, X1 is greater than or equal to X2.

    Semiconductor device and method of manufacturing the same
    112.
    发明授权
    Semiconductor device and method of manufacturing the same 有权

    公开(公告)号：US10861855B2

    公开(公告)日：2020-12-08

    申请号：US16841702

    申请日：2020-04-07

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Shih-Fang Tzou ,  Chien-Cheng Tsai ,  Chih-Chi Cheng ,  Chia-Wei Wu ,  Ger-Pin Lin

    IPC: H01L27/108

    Abstract: A semiconductor device and method of manufacturing the same is provided in the present invention. The method includes the step of forming first mask patterns on a substrate, wherein the first mask patterns extend in a second direction and are spaced apart in a first direction to expose a portion of first insulating layer, removing the exposed first insulating layer to form multiple recesses in the first insulating layer, performing a surface treatment to the recess surface, filling up the recesses with a second insulating layer and exposing a portion of the first insulating layer, removing the exposed first insulating layer to form a mesh-type isolation structure, and forming storage node contact plugs in the openings of mesh-type isolation structure.

    Semiconductor memory device including gate structure
    116.
    发明授权
    Semiconductor memory device including gate structure 有权

    公开(公告)号：US10665594B2

    公开(公告)日：2020-05-26

    申请号：US16036908

    申请日：2018-07-16

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Li-Wei Feng ,  Ying-Chiao Wang ,  Shih-Fang Tzou

    IPC: H01L29/49 ,  H01L27/108 ,  H01L23/535 ,  H01L29/423 ,  H01L29/66

    Abstract: A semiconductor memory device includes a semiconductor substrate, a gate structure, a first spacer structure, and a gate connection structure. The semiconductor substrate includes a memory cell region and a peripheral region. The gate structure is disposed on the semiconductor substrate and disposed on the peripheral region. The gate structure includes a first conductive layer and a gate capping layer. The gate capping layer is disposed on the first conductive layer. The first spacer structure is disposed on a sidewall of the first conductive layer and a sidewall of the gate capping layer. The gate connection structure includes a first part and a second part. The first part penetrates the gate capping layer and is electrically connected with the first conductive layer. The second part is connected with the first part, and the second part is disposed on and contacts a top surface of the gate capping layer.

    Semiconductor memory device
    117.
    发明授权
    Semiconductor memory device 有权

    公开(公告)号：US10553591B2

    公开(公告)日：2020-02-04

    申请号：US16294934

    申请日：2019-03-07

    Applicant: UNITED MICROELECTRONICS CORP. ,  Fujian Jinhua Integrated Circuit Co., Ltd.

    Inventor： Ying-Chiao Wang ,  Li-Wei Feng ,  Chien-Ting Ho

    IPC: H01L29/76 ,  H01L29/94 ,  H01L27/108

    Abstract: A semiconductor memory device and a manufacturing method thereof are provided. At least one bit line structure including a first metal layer, a bit line capping layer, and a first silicon layer located between the first metal layer and the bit line capping layer is formed on a semiconductor substrate. A bit line contact opening penetrating the bit line capping layer is formed for exposing a part of the first silicon layer. A first metal silicide layer is formed on the first silicon layer exposed by the bit line contact opening. A bit line contact structure is formed in the bit line contact opening and contacts the first metal silicide layer for being electrically connected to the bit line structure. The first silicon layer in the bit line structure may be used to protect the first metal layer from being damaged by the process of forming the metal silicide layer.

Patent Agency Ranking