知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

123 records (took 0.027 seconds)

    PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA
    111.
    发明申请
    PROTECTION LINER ON INTERCONNECT WIRE TO ENLARGE PROCESSING WINDOW FOR OVERLYING INTERCONNECT VIA 有权

    公开(公告)号：US20210398898A1

    公开(公告)日：2021-12-23

    申请号：US16908942

    申请日：2020-06-23

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Hsin-Yen Huang ,  Ming-Han Lee ,  Shau-Lin Shue ,  Yu-Chen Chan ,  Meng-Pei Lu

    IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a lower dielectric arranged over a substrate. An interconnect wire is arranged over the dielectric layer, and a first interconnect dielectric layer is arranged outer sidewalls of the interconnect wire. A protection liner that includes graphene is arranged directly on the outer sidewalls of the interconnect wire and on a top surface of the interconnect wire. The integrated chip further includes a first etch stop layer arranged directly on upper surfaces of the first interconnect dielectric layer, and a second interconnect dielectric layer arranged over the first interconnect dielectric layer and the interconnect wire. Further, an interconnect via extends through the second interconnect dielectric layer, is arranged directly over the protection liner, and is electrically coupled to the interconnect wire.

    Graphene barrier layer
    112.
    发明授权
    Graphene barrier layer 有权

    公开(公告)号：US11205618B2

    公开(公告)日：2021-12-21

    申请号：US16571279

    申请日：2019-09-16

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shin-Yi Yang ,  Ming-Han Lee ,  Shau-Lin Shue

    IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L21/324

    Abstract: Interconnect structures and method of forming the same are disclosed herein. An exemplary interconnect structure includes a first contact feature in a first dielectric layer, a second dielectric layer over the first dielectric layer, a third dielectric layer over the second dielectric layer, a second contact feature extending through the second dielectric layer and the third dielectric layer, and a graphene layer between the second contact feature and the third dielectric layer.

    INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP
    114.
    发明申请
    INTERCONNECT STRUCUTRE WITH PROTECTIVE ETCH-STOP 有权

    公开(公告)号：US20210358803A1

    公开(公告)日：2021-11-18

    申请号：US16876465

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Shao-Kuan Lee ,  Hai-Ching Chen ,  Hsin-Yen Huang ,  Shau-Lin Shue ,  Cheng-Chin Lee

    IPC: H01L21/768 ,  H01L23/535 ,  H01L23/532

    Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip may comprise a first metal line disposed over a substrate. A via may be disposed directly over a top of the first metal line and the via may comprise a first lower surface and a second lower surface above the first lower surface. A first dielectric structure may be disposed laterally adjacent to the first metal line and may be disposed along a sidewall of the first metal line. A first protective etch-stop structure may be disposed directly over a top of the first dielectric structure and the first protective etch-stop structure may vertically separate the second lower surface of the via from the top of the first dielectric structure.

    DIELECTRIC CAPPING STRUCTURE OVERLYING A CONDUCTIVE STRUCTURE TO INCREASE STABILITY
    117.
    发明申请
    DIELECTRIC CAPPING STRUCTURE OVERLYING A CONDUCTIVE STRUCTURE TO INCREASE STABILITY 有权

    公开(公告)号：US20210193505A1

    公开(公告)日：2021-06-24

    申请号：US16876432

    申请日：2020-05-18

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hsin-Yen Huang ,  Chi-Lin Teng ,  Hai-Ching Chen ,  Shau-Lin Shue ,  Shao-Kuan Lee ,  Cheng-Chin Lee ,  Ting-Ya Lo

    IPC: H01L21/768 ,  H01L23/532

    Abstract: Some embodiments relate to a semiconductor structure including a first inter-level dielectric (ILD) structure overlying a substrate. A conductive contact directly overlies the substrate and is disposed within the first ILD structure. A conductive wire directly overlies the conductive contact. A conductive capping layer overlies the conductive wire such that the conductive capping layer continuously extends along an upper surface of the conductive wire. A second ILD structure overlies the conductive capping layer. The second ILD structure is disposed along opposing sides of the conductive wire. A pair of air-gaps are disposed within the second ILD structure. The conductive wire is spaced laterally between the pair of air-gaps. A dielectric capping layer is disposed along an upper surface of the conductive capping layer. The dielectric capping layer is spaced laterally between the pair of air-gaps and is laterally offset from an upper surface of the first ILD structure.

    Structure and method for interconnection with self-alignment
    119.
    发明授权
    Structure and method for interconnection with self-alignment 有权

    公开(公告)号：US11004740B2

    公开(公告)日：2021-05-11

    申请号：US16560717

    申请日：2019-09-04

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Tai-I Yang ,  Yu-Chieh Liao ,  Chia-Tien Wu ,  Hsin-Ping Chen ,  Hai-Ching Chen ,  Shau-Lin Shue

    IPC: H01L21/768 ,  H01L21/311 ,  H01L21/3213 ,  H01L23/532 ,  H01L23/522 ,  H01L21/3105

    Abstract: The present disclosure provides a method of forming an integrated circuit structure. The method includes depositing a first metal layer on a semiconductor substrate; forming a hard mask on the first metal layer; patterning the first metal layer to form first metal features using the hard mask as an etch mask; depositing a dielectric layer of a first dielectric material on the first metal features and in gaps among the first metal features; performing a chemical mechanical polishing (CMP) process to both the dielectric layer and the hard mask; removing the hard mask, thereby having portions of the dielectric layer extruded above the metal features; forming an inter-layer dielectric (ILD) layer of the second dielectric material different from the first dielectric material; and patterning the ILD layer to form openings that expose the first metal features and are constrained to be self-aligned with the first metal features by the extruded portions of the first dielectric layer.

Patent Agency Ranking