公开(公告)号：US20150070369A1

公开(公告)日：2015-03-12

申请号：US14023170

申请日：2013-09-10

Applicant: QUALCOMM Incorporated

Inventor： Christopher Paul Frascati ,  Murat Balci ,  Avinash Seetharamaiah ,  Andrew Evan Gruber ,  Alexei Vladimirovich Bourd

IPC: G09G5/399

CPC classification number: G09G5/399 ,  G06F9/46 ,  G06F9/4843 ,  G06F2209/483 ,  G06F2209/509 ,  G06T1/20 ,  G06T1/60

Abstract: This disclosure presents techniques and structures for preemption at arbitrary control points in graphics processing. A method of graphics processing may comprise executing commands in a command buffer, the commands operating on data in a read-modify-write memory resource, double buffering the data in the read-modify-write memory resource, such that a first buffer stores original data of the read-modify-write memory resource and a second buffer stores any modified data produced by executing the commands in the command buffer, receiving a request to preempt execution of the commands in the command buffer before completing all commands in the command buffer, and restarting execution of the commands at the start of the command buffer using the original data in the first buffer.

Abstract translation: 本公开提供在图形处理中的任意控制点处的抢占的技术和结构。 图形处理的方法可以包括在命令缓冲器中执行命令，操作在读 - 修改 - 写存储器资源中的数据的命令，双重缓冲读 - 修改 - 写存储器资源中的数据，使得第一缓冲器存储原始 读取 - 修改 - 写入存储器资源的数据和第二缓冲器存储通过在命令缓冲器中执行命令而产生的任何修改的数据，在完成命令缓冲器中的所有命令之前接收到抢占命令缓冲器中的命令执行的请求， 并使用第一缓冲器中的原始数据重新启动命令缓冲区开始处的命令。

公开(公告)号：US20140267259A1

公开(公告)日：2014-09-18

申请号：US13841584

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Christopher Paul Frascati ,  Avinash Seetharamaiah ,  Andrew Evan Gruber

IPC: G06T17/20

CPC classification number: G06T15/005

Abstract: This disclosure describes techniques for using bounding regions to perform tile-based rendering with a graphics processing unit (GPU) that supports an on-chip, tessellation-enabled graphics rendering pipeline. Instead of generating binning data based on rasterized versions of the actual primitives to be rendered, the techniques of this disclosure may generate binning data based on a bounding region that encompasses one or more of the primitives to be rendered. Moreover, the binning data may be generated based on data that is generated by at least one tessellation processing stage of an on-chip, tessellation-enabled graphics rendering pipeline that is implemented by the GPU. The techniques of this disclosure may, in some examples, be used to improve the performance of an on-chip, tessellation-enabled GPU when performing tile-based rendering without sacrificing the quality of the resulting rendered image.

Abstract translation: 本公开描述了使用边界区域来执行基于瓦片的渲染的技术，该图形处理单元（GPU）支持片上，镶嵌的图形渲染流水线。 基于要渲染的实际原语的光栅化版本而不是生成合并数据，本公开的技术可以基于包含要呈现的一个或多个基元的边界区域来生成合并数据。 此外，可以基于由GPU实现的片上，镶嵌使能的图形呈现流水线的至少一个镶嵌处理阶段生成的数据来生成合并数据。 在一些示例中，本公开的技术可以用于在不牺牲所得到的渲染图像的质量的情况下执行基于图块的渲染时，提高片上，镶嵌功能的GPU的性能。

公开(公告)号：US20140040552A1

公开(公告)日：2014-02-06

申请号：US13958399

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Bohuslav Rychlik ,  Tzung Ren Tzeng ,  Andrew Evan Gruber ,  Alexei V. Bourd ,  Colin Christopher Sharp ,  Eric Demers

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/0833 ,  G06F12/0837 ,  G06F12/0891 ,  G06F2212/302

Abstract: A method includes storing, with a first programmable processor, shared variable data to cache lines of a first cache of the first processor. The method further includes executing, with the first programmable processor, a store-with-release operation, executing, with a second programmable processor, a load-with-acquire operation, and loading, with the second programmable processor, the value of the shared variable data from a cache of the second programmable processor.

Abstract translation: 一种方法包括使用第一可编程处理器将共享变量数据存储到第一处理器的第一高速缓存的高速缓存行。 该方法还包括利用第一可编程处理器执行存储释放操作，利用第二可编程处理器执行带有采集操作的负载，并且与第二可编程处理器一起执行共享的值 来自第二可编程处理器的缓存的可变数据。