公开(公告)号：US20090162713A1

公开(公告)日：2009-06-25

申请号：US12047627

申请日：2008-03-13

Applicant: Jie PENG ,  Jae-Young Shin ,  Seung-Jae Lee

Inventor： Jie PENG ,  Jae-Young Shin ,  Seung-Jae Lee

IPC: H01M8/02 ,  F28D15/00

CPC classification number: H01M2/1083 ,  F28F3/12

Abstract: Provided is a stack of a fuel cell in which a plurality of unit cells are stacked to perform an electricity generation reaction. The stack includes a membrane electrode assembly in which an anode, an electricity membrane, and a cathode are stacked; a bipolar plate having reactant channels through which fluids to be supplied to the anode and the cathode flow and a plurality of inner manifolds that are formed in positions not directly connected to the reactant channels so that a coolant pass through; and a cooling plate having a coolant channels through which a coolant flows and a plurality of inner manifolds that are formed corresponding to the inner manifolds of the bipolar plate so that the coolant pass through.

Abstract translation: 提供了堆叠多个单位电池进行发电反应的燃料电池的堆叠。 堆叠包括其中堆叠阳极，电膜和阴极的膜电极组件; 具有反应物通道的双极板，待供应到阳极和阴极流的流体和多个内歧管，其形成在不直接连接到反应物通道的位置，使得冷却剂通过; 以及具有冷却剂流过的冷却剂通道的冷却板和对应于双极板的内部歧管形成的多个内部歧管，使得冷却剂通过。

公开(公告)号：US20090158437A1

公开(公告)日：2009-06-18

申请号：US12092536

申请日：2006-10-31

Applicant: Te-Hyun Kim ,  Seung-Jae Lee

Inventor： Te-Hyun Kim ,  Seung-Jae Lee

IPC: G06F21/00

CPC classification number: H04L9/0825 ,  H04L9/0891 ,  H04L63/06 ,  H04L63/0853 ,  H04L2209/603 ,  H04L2463/101

Abstract: A digital rights management (DRM) method and system between devices are disclosed. In order to allow a first device connected with a second device to use a rights object (RO) bound to the second device, the second device decodes the particular content or the RO and transmits the decoded particular content or the decoded RO to the first device. State information of the RO according to a usage amount of the particular content used by the first device is managed by the second device.

Abstract translation: 披露了设备之间的数字版权管理（DRM）方法和系统。 为了允许与第二设备连接的第一设备使用与第二设备绑定的权限对象（RO），第二设备对特定内容或RO进行解码，并将解码的特定内容或解码的RO发送到第一设备 。 根据第一设备使用的特定内容的使用量的RO的状态信息由第二设备管理。

公开(公告)号：US07512020B2

公开(公告)日：2009-03-31

申请号：US11319324

申请日：2005-12-27

Applicant: Seung-Jae Lee

Inventor： Seung-Jae Lee

IPC: G11C7/10

CPC classification number: G11C16/3459 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3454

Abstract: A nonvolatile semiconductor memory device includes an internal output line, and a page buffers. Each page buffer is coupled to at least one bitline, the internal output line, and a data input line physically distinct from the internal output line, and configured to pull the internal output line to an output drive voltage in response to a bitline voltage on one of the bitlines coupled to the page buffer.

Abstract translation: 非易失性半导体存储器件包括内部输出线和页缓冲器。 每个页缓冲器耦合到至少一个位线，内部输出线和物理上不同于内部输出线的数据输入线，并且被配置为响应于一个位线电压将内部输出线拉到输出驱动电压 的位线耦合到页面缓冲区。

公开(公告)号：US07442607B2

公开(公告)日：2008-10-28

申请号：US11533273

申请日：2006-09-19

Applicant: Min Kim ,  Ju-Bum Lee ,  Hyeong-Deok Lee ,  Seung-Jae Lee

Inventor： Min Kim ,  Ju-Bum Lee ,  Hyeong-Deok Lee ,  Seung-Jae Lee

IPC: H01L21/00

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract translation: 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20080155646A1

公开(公告)日：2008-06-26

申请号：US11911709

申请日：2006-05-23

Applicant: Seung-Jae Lee

Inventor： Seung-Jae Lee

IPC: G06F21/00

CPC classification number: G06F21/10 ,  G06F2221/2135 ,  G06F2221/2137

Abstract: Provided are a rights object, a rights object issuing method, and a contents controlling method using the same, wherein when a Digital Rights Management (DRM) having received a request for operating a certain content receives a rights object including pre-use constraint information with respect to another content in order to use the corresponding certain content, the DRM agent operates the corresponding content if every operation designated in the pre-use constraint information or at least one or more of the operations are performed to thus satisfy the constraint.

Abstract translation: 提供了一种权利对象，权利对象发布方法和使用该权利对象发布方法的内容控制方法，其中当已经接收到用于操作某个内容的操作的请求的数字版权管理（DRM）接收到包括预先使用的约束信息的权利对象时， 为了使用相应的特定内容，DRM代理操作相应的内容，如果执行在预先使用约束信息中指定的每个操作或执行至少一个或多个操作以满足约束条件。

公开(公告)号：US20070038576A1

公开(公告)日：2007-02-15

申请号：US11502460

申请日：2006-08-11

Applicant: Seung-Jae Lee

Inventor： Seung-Jae Lee

IPC: G06Q99/00

CPC classification number: H04L63/065 ,  G06F21/10 ,  G06F2221/0786 ,  H04L63/0428 ,  H04L63/104 ,  H04L2463/101

Abstract: A method for moving Rights Object (RO) in a Digital Rights Management (DRM). RO for content is partially or entirely moved between Devices in the same group, so that the RO can be shared between the Devices and a utility thereof can be enhanced.

Abstract translation: 一种在数字版权管理（DRM）中移动权限对象（RO）的方法。 用于内容的RO部分或全部在同一组中的设备之间移动，从而可以在设备之间共享RO，并且可以增强其效用。

公开(公告)号：US20070028155A1

公开(公告)日：2007-02-01

申请号：US11363030

申请日：2006-02-28

Applicant: Moo-Sung Kim ,  Seung-Jae Lee

Inventor： Moo-Sung Kim ,  Seung-Jae Lee

IPC: H03M13/00

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5622 ,  G11C2216/14

Abstract: A flash memory device is disclosed that comprises memory cells, a sense node connected to a selected bit line, a sense circuit configured to selectively provide a first voltage to a common node in accordance with a voltage level of the sense node, a first register connected to the sense node and the common node and configured to store data in accordance with a voltage level of the common node,a second register configured to store data in accordance with the voltage level of the sense node, a switch configured to provide a second voltage to the second register, and a discharge circuit configured to selectively discharge the sense node in accordance with the data stored in the second register.

Abstract translation: 公开了一种闪速存储器件，其包括存储器单元，连接到所选位线的感测节点，感测电路，被配置为根据感测节点的电压电平有选择地向公共节点提供第一电压;第一寄存器连接 到所述感测节点和所述公共节点，并且被配置为根据所述公共节点的电压电平来存储数据;第二寄存器，被配置为根据所述感测节点的电压电平来存储数据;被配置为提供第二电压 以及放电电路，其被配置为根据存储在第二寄存器中的数据选择性地放电感测节点。

公开(公告)号：US20070020882A1

公开(公告)日：2007-01-25

申请号：US11533273

申请日：2006-09-19

Applicant: Min Kim ,  Ju-Bum Lee ,  Hyeong-Deok Lee ,  Seung-Jae Lee

Inventor： Min Kim ,  Ju-Bum Lee ,  Hyeong-Deok Lee ,  Seung-Jae Lee

IPC: H01L21/76

CPC classification number: H01L29/66621 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/823487 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7835

Abstract: A method of fabricating a transistor with a recessed channel is provided. The method includes forming trenches for a recessed channel on a semiconductor substrate, depositing an isolation layer on the semiconductor substrate on which the trenches are formed, depositing a gate dielectric layer on the semiconductor substrate so that the gate dielectric layer can be extended to bottoms and sidewalls of the trenches, forming gates to fill the trenches, and forming source and drain regions in the semiconductor substrate adjacent to the gates.

Abstract translation: 提供一种制造具有凹槽的晶体管的方法。 该方法包括在半导体衬底上形成用于凹陷沟道的沟槽，在其上形成有沟槽的半导体衬底上沉积隔离层，在半导体衬底上沉积栅极电介质层，使得栅极电介质层可以延伸到底部， 沟槽的侧壁，形成用于填充沟槽的栅极，以及在与栅极相邻的半导体衬底中形成源区和漏区。

公开(公告)号：US20060109715A1

公开(公告)日：2006-05-25

申请号：US11285273

申请日：2005-11-22

Applicant: Seung-Jae Lee ,  Jung-Hoon Park

Inventor： Seung-Jae Lee ,  Jung-Hoon Park

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C29/846

Abstract: A NAND flash memory device according to the present invention is provided which includes a first page buffer circuit reading main data bits from the main field during a read operation, a second page buffer circuit reading redundant data bits from the redundancy field during the read operation, a first column gate circuit configured to select a part of the read main data bits and a part of the read redundant data bits in response to first column selection signals at the same time, and a second column gate circuit configured to select a part of the selected main data bits in response to second column selection signals.

Abstract translation: 提供了根据本发明的NAND闪速存储器件，其包括在读操作期间从主场读取主数据位的第一页缓冲电路，在读操作期间从冗余字段读取冗余数据位的第二页缓冲电路， 第一列门电路，被配置为响应于第一列选择信号同时选择读取的主数据位的一部分和读取的冗余数据位的一部分;以及第二列门电路，被配置为选择一部分 选择的主数据位响应于第二列选择信号。

公开(公告)号：US20050114048A1

公开(公告)日：2005-05-26

申请号：US10722089

申请日：2003-11-25

Applicant: Myoen-Song Choi ,  Seung-Jae Lee

Inventor： Myoen-Song Choi ,  Seung-Jae Lee

IPC: G01R31/08 ,  H02H1/00 ,  H02H3/40 ,  G06F19/00

CPC classification number: H02H1/0092 ,  G01R31/088 ,  H02H3/40

Abstract: The present invention relates to a method for detecting a line-to-line fault location in power network, and more particularly, detecting the line-to-line fault location by direct 3-phase circuit analysis without using a symmetrical component transformation, so even in an unbalanced 3-phase circuit, the line-to-line fault location can be accurately detected. In the method using direct 3-phase circuit analysis of this invention, inverse lemma is used to simplify matrix inversion calculations, thus the line-to-line fault location can be easily and accurately determined even in the case of an unbalanced network without symmetrical component transformation.

Abstract translation: 本发明涉及一种用于检测电力线路中线路故障定位的方法，更具体地，涉及通过直接三相电路分析检测线间故障定位而不使用对称分量变换， 在不平衡的三相电路中，可以准确地检测到线路故障位置。 在使用本发明的直接三相电路分析的方法中，使用逆引理来简化矩阵反演计算，因此即使在不对称分量的不平衡网络的情况下也可以容易且准确地确定线对线故障位置 转型。