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公开(公告)号:US12142220B2
公开(公告)日:2024-11-12
申请号:US18532835
申请日:2023-12-07
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Shih Chang Chang , Shinya Ono
IPC: G09G3/3233 , G09G3/3266 , G09G3/3275 , H01L27/12 , H01L29/786
Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
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公开(公告)号:US20240312421A1
公开(公告)日:2024-09-19
申请号:US18673126
申请日:2024-05-23
Applicant: Apple Inc.
Inventor: Shinya Ono , Chin-Wei Lin , Pei-En Chang , Dongqi Zheng
IPC: G09G3/3266 , G09G3/3233 , G11C19/28
CPC classification number: G09G3/3266 , G11C19/28 , G09G3/3233 , G09G2300/0842 , G09G2310/0286 , G09G2310/0291 , G09G2310/08
Abstract: A display may include an array of pixels that receive control signals from a chain of gate drivers. Each gate driver may include a shift register subcircuit and an output buffer subcircuit. The shift register subcircuit may include a first set of transistors at least partially controlled by one or more shift register clock signals. The output buffer subcircuit may include a second set of transistors at least partially controlled by one or more output buffer clock signals. The output buffer clock signals can toggle independently from the shift register clock signals. Operated in this way, the shift register clock signals can have pulse widths optimized for stability while the output buffer clock signals can have pulse widths optimized for speed.
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公开(公告)号:US12096657B2
公开(公告)日:2024-09-17
申请号:US17504230
申请日:2021-10-18
Applicant: Apple Inc.
Inventor: Jung Yen Huang , Shinya Ono , Chin-Wei Lin , Akira Matsudaira , Cheng Min Hu , Chih Pang Chang , Ching-Sang Chuang , Gihoon Choo , Jiun-Jye Chang , Po-Chun Yeh , Shih Chang Chang , Yu-Wen Liu , Zino Lee
IPC: H01L27/32 , H01L29/66 , H01L29/786 , H10K59/121 , H10K59/12
CPC classification number: H10K59/1213 , H01L29/66742 , H01L29/7869 , H10K59/1216 , H10K59/1201
Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to associated semiconducting oxide transistors. The semiconducting oxide transistors may exhibit different device characteristics. Some of the semiconducting oxide transistors may be formed using a first oxide layer formed from a first semiconducting oxide material using first processing steps, whereas other semiconducting oxide transistors are formed using a second oxide layer formed from a second semiconducting oxide material using second processing steps different than the first processing steps. The display may include three or more different semiconducting oxide layers formed during different processing steps.
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公开(公告)号:US20230260452A1
公开(公告)日:2023-08-17
申请号:US18306690
申请日:2023-04-25
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Vasudha Gupta , Shinya Ono , Tsung-Ting Tsai , Shyuan Yang
IPC: G09G3/32 , G09G3/3233 , G09G3/3291
CPC classification number: G09G3/32 , G09G3/3233 , G09G3/3291 , G09G2330/021 , G09G2340/0435 , G09G2320/0247 , G09G2310/0251 , G09G2310/061 , G09G2300/0842 , G09G2300/0861 , G09G2310/0297
Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
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公开(公告)号:US11670219B2
公开(公告)日:2023-06-06
申请号:US17204803
申请日:2021-03-17
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Vasudha Gupta , Shinya Ono , Tsung-Ting Tsai , Shyuan Yang
IPC: G09G3/32 , G09G3/3233 , G09G3/3291
CPC classification number: G09G3/32 , G09G3/3233 , G09G3/3291 , G09G2300/0842 , G09G2300/0861 , G09G2310/0251 , G09G2310/0297 , G09G2310/061 , G09G2320/0247 , G09G2330/021 , G09G2340/0435
Abstract: An electronic device comprises a display and a controller. The controller is configured to provide a first frequency refresh rate to the display. The controller is also configured to generate a control signal configured to control emission of a light emitting diode of a display pixel of the display at a second frequency based on whether the first frequency refresh rate of the display is less than a predetermined threshold value.
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公开(公告)号:US20230080809A1
公开(公告)日:2023-03-16
申请号:US17990510
申请日:2022-11-18
Applicant: Apple Inc.
Inventor: Shinya Ono , Chin-Wei Lin , Zino Lee , Chun-Chieh Lin , Chen-Ming Chen
IPC: G09G3/3291 , G09G3/3266
Abstract: A display may include an array of pixels. Each pixel in the array includes an organic light-emitting diode coupled to a drive transistor, a data loading transistor, a first capacitor for storing data charge, and a second capacitor. During a data programming phase, the data loading transistor may be activated to load in a data value onto the first capacitor. After the data programming phase, the second capacitor may be configured to receive a lower voltage, which extends a threshold voltage sampling time for the pixel. Configured and operated in this way, the temperature luminance sensitivity of the display can be reduced.
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公开(公告)号:US20220383817A1
公开(公告)日:2022-12-01
申请号:US17884297
申请日:2022-08-09
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Shih Chang Chang , Shinya Ono
IPC: G09G3/3233 , H01L29/786 , G09G3/3266 , G09G3/3275 , H01L27/12
Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
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公开(公告)号:US11488538B1
公开(公告)日:2022-11-01
申请号:US17213041
申请日:2021-03-25
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Shinya Ono , Gihoon Choo
IPC: G09G3/3266
Abstract: A display is provided that includes an array of display pixels that receive data signals from display driver circuitry and that receive control signals from gate driver circuitry. The gate driver circuitry may include a chain of row driver circuits. Each row driver circuit may include a scan driver circuit and a scan inverter circuit. An enable transistor may be interposed between the scan driver circuit and the scan inverter circuit and may be selectively disabled to decouple the scan inverter circuit from the scan driver circuit to allow the scan inverter circuit to operate independent from the scan driver circuit. The scan inverter circuit may include a transistor that receives a scan pulse signal from the scan driver circuit and may further include additional transistors connected in a negative feedback configuration to reduce a drain-to-source voltage across the transistor to reduce leakage across the transistor during blanking times.
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公开(公告)号:US20220114962A1
公开(公告)日:2022-04-14
申请号:US17555694
申请日:2021-12-20
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Hung Sheng Lin , Shih Chang Chang , Shinya Ono
IPC: G09G3/3233 , H01L29/786 , G09G3/3266 , G09G3/3275 , H01L27/12
Abstract: A display may have an array of pixels each of which has a light-emitting diode such as an organic light-emitting diode. A drive transistor and an emission transistor may be coupled in series with the light-emitting diode of each pixel between a positive power supply and a ground power supply. The pixels may include first and second switching transistors. A data storage capacitor may be coupled between a gate and source of the drive transistor in each pixel. Signal lines may be provided in columns of pixels to route signals such as data signals, sensed drive currents from the drive transistors, and predetermined voltages between display driver circuitry and the pixels. The switching transistors, emission transistors, and drive transistors may include semiconducting-oxide transistors and silicon transistors and may be n-channel transistors or p-channel transistors.
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公开(公告)号:US11282462B2
公开(公告)日:2022-03-22
申请号:US17062786
申请日:2020-10-05
Applicant: Apple Inc.
Inventor: Chin-Wei Lin , Shinya Ono , Zino Lee , Yun Wang , Fan Gui
IPC: G09G3/3258 , H01L27/32 , H01L29/786
Abstract: A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.
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