公开(公告)号：US11164541B2

公开(公告)日：2021-11-02

申请号：US16711322

申请日：2019-12-11

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Mahesh B. Chappalli

IPC: G09G3/16 ,  G09G5/10

Abstract: An electronic device may include an electronic display to display images during frames based on image data. The electronic display may be divided into multiple regions each having multiple pixels. The electronic device may also include a display pipeline to process the image data and output the processed image data to the electronic display. The display pipeline may also determine a history update corresponding to an estimated burn-in aging effect of the pixels based on usage. A first portion of the history update corresponding to pixels in a first region may be determined during a first frame and a second portion of the history update corresponding to pixels in a second region may be determined during a second frame.

公开(公告)号：US20210183334A1

公开(公告)日：2021-06-17

申请号：US16711322

申请日：2019-12-11

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Mahesh B. Chappalli

IPC: G09G5/10

Abstract: An electronic device may include an electronic display to display images during frames based on image data. The electronic display may be divided into multiple regions each having multiple pixels. The electronic device may also include a display pipeline to process the image data and output the processed image data to the electronic display. The display pipeline may also determine a history update corresponding to an estimated burn-in aging effect of the pixels based on usage. A first portion of the history update corresponding to pixels in a first region may be determined during a first frame and a second portion of the history update corresponding to pixels in a second region may be determined during a second frame.

公开(公告)号：US20200349046A1

公开(公告)日：2020-11-05

申请号：US16401364

申请日：2019-05-02

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Hari Ganesh R. Thirunageswaram

IPC: G06F11/30 ,  H03K3/3565 ,  H03K19/0175 ,  G06F13/40

Abstract: In an embodiment, an integrated circuit includes one or more GPIO pins coupled to a GPIO block in the integrated circuit. At least a first GPIO pin may include corresponding logic circuitry that may be programmed to apply one or more requirements to changes of the digital value received on the first GPIO pin before the change is forwarded to a destination within the integrated circuit. That is, if the requirements are not met for a given change, the logic circuitry may suppress the given change so that it is not provided to other circuits internal to the integrated circuit (e.g. the destination circuit that receives communication via the GPIO pins). The one or more requirements may be a form of hysteresis, for example.

公开(公告)号：US20200227010A1

公开(公告)日：2020-07-16

申请号：US16828824

申请日：2020-03-24

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Mahesh B. Chappalli ,  Assaf Menachem

IPC: G09G5/393 ,  G09G5/10 ,  G09G5/395

Abstract: An electronic device may include a display panel and an image data source designed to determine a differing region in the image frame by comparing source image data and image data corresponding with a previous image frame. The electronic device may also include a display pipeline between the image data source and the display panel. The display pipeline may include image processing circuitry to convert image data from a source space to a display space and image processing circuitry to spatially process the image data. The display pipeline may determine a crop region by converting the differing region to the display space and determine a partial frame region, based on the image data to be spatially processed, by the image processing circuitry. The display pipeline may also determine and retrieve a fetch region smaller than the image frame by converting the partial frame region to the source space.

公开(公告)号：US20200081517A1

公开(公告)日：2020-03-12

申请号：US16123848

申请日：2018-09-06

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Brad W. Simeral ,  Lior Zimet

IPC: G06F1/32

Abstract: An electronic device may include a display panel to display images based on corresponding image data and an image source to pre-render a flip-book including a first image frame for display at a first target presentation time and a second image frame for display at a second target presentation time. The electronic device may also include a display pipeline coupled between the display panel and the image source having image data processing circuitry to process image data for display. The electronic device may also include a controller to instruct the display pipeline to process image data, to determine a power-on time based on a target presentation time, and to instruct the display pipeline to power-gate the image data processing circuitry upon completion of the processing of image data and until the power-on time is reached.

公开(公告)号：US20200074583A1

公开(公告)日：2020-03-05

申请号：US16122473

申请日：2018-09-05

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Mahesh B. Chappalli

IPC: G06T1/20 ,  G06T1/60 ,  G06F13/28 ,  G06F12/1081

Abstract: Display pipeline may manage allocation of total memory bandwidth to memory access requester blocks (e.g., display pipeline as a whole and/or a block in the display pipeline) by dynamically allocating the total memory bandwidth based at least in part on a calculated bandwidth floor to reduce the communication inefficiency (e.g., underruns), excessive power consumption, and image quality degradation of the display pipeline. Image fetch parameters, electronic display parameters, display pipeline parameters, and memory access requester block parameters may be used to determine the appropriate bandwidth floor for each memory access requester of the display pipeline. Additional memory bandwidth may be allocated to memory access requesters of the display pipeline when available bandwidth remains to further reduce likelihood of subsequent communication inefficiencies in the display pipeline.

公开(公告)号：US10546558B2

公开(公告)日：2020-01-28

申请号：US14262298

申请日：2014-04-25

Applicant: Apple Inc.

Inventor： Marc A. Schaub ,  Jeffrey J. Irwin ,  Peter F. Holland

IPC: G09G5/36

Abstract: Systems, apparatuses, and methods for aggregating memory requests with opportunism in a display pipeline. Memory requests are aggregated for each requestor of a plurality of requestors in the display pipeline. When the number of memory requests for a given requestor reaches a corresponding threshold, memory requests may be issued for the given requestor. In response to determining the given requestor has reached its threshold, other requestors may issue memory requests even if they have not yet aggregated enough memory requests to reach their corresponding thresholds.

公开(公告)号：US10013046B2

公开(公告)日：2018-07-03

申请号：US15150109

申请日：2016-05-09

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Hao Chen ,  Sukalpa Biswas

IPC: G06F3/038 ,  G06F1/32 ,  G09G5/00

CPC classification number: G06F1/3265 ,  G06F1/3206 ,  G06F1/3218 ,  G06F1/3225 ,  G06F1/3287 ,  G09G5/006 ,  G09G2330/021 ,  G09G2330/026 ,  G09G2340/06 ,  G09G2360/121

Abstract: Systems, apparatuses, and methods for improved power management techniques. An apparatus may include a display control unit, a communication fabric, a memory controller, a memory cache, and a memory. When the memory is power-gated, and the display control unit needs to fetch pixel data, the display control unit may send a wake-up signal to the memory before sending a wake-up signal to the communication fabric. The display control unit may then issue the pixel fetch request later. Additionally, if the display control unit determines that the pixel data has a high probability of being cached, then the display control unit may not send a wake-up signal to the memory, and the display control unit may issue the request earlier. More generally, the display control unit may send wake-up signals to multiple components in a manner which accounts for the wake-up latency of each component.

公开(公告)号：US09558536B2

公开(公告)日：2017-01-31

申请号：US14676615

申请日：2015-04-01

Applicant: Apple Inc.

Inventor： Peter F. Holland ,  Eric Young ,  Guy Cote

IPC: G06K9/40 ,  G06T5/00 ,  G06T3/40

CPC classification number: G06T5/002 ,  G06T3/4023

Abstract: Systems, apparatuses, and methods for generating a blur effect on a source image in a power-efficient manner. Pixels of the source image are averaged as they are read into pixel buffers, and then the source image is further downscaled by a first factor. Then, the downscaled source image is upscaled back to the original size, and then this processed image is composited with a semi-transparent image to create a blurred effect of the source image.

Abstract translation: 以功率有效的方式在源图像上产生模糊效果的系统，装置和方法。 源图像的像素在被读取到像素缓冲器中时被平均，然后源图像被第一因子进一步缩小。 然后，将缩小的源图像放大到原始尺寸，然后将该处理后的图像与半透明图像合成，以产生源图像的模糊效果。

公开(公告)号：US20170018247A1

公开(公告)日：2017-01-19

申请号：US14799855

申请日：2015-07-15

Applicant: Apple Inc.

Inventor： Jeffrey E. Frederiksen ,  Peter F. Holland

IPC: G09G5/00

CPC classification number: G09G5/395 ,  G09G5/39 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2340/02 ,  G09G2340/0407 ,  G09G2340/10 ,  G09G2350/00 ,  G09G2360/121

Abstract: A system and method for display frame compression and write to memory are disclosed. A display pipe is configured to generate frames for display. Additionally, the display pipe may be configured to initiate compression of a frame prior to detection of an idle condition. The display pipe may also be configured to determine to selectively allow write-back logic to operate responsive to detecting various conditions. The display pipe may compress a frame and compare the size of the frame as compressed to a threshold value. If the size of the compressed frame exceeds the threshold value, write back of the compressed frame to memory is prevented. Write back of the compressed frame may be further conditioned on the detection of other conditions.

Abstract translation: 公开了一种用于显示帧压缩和写入存储器的系统和方法。 显示管被配置为生成用于显示的帧。 另外，显示管可以被配置为在检测到空闲状态之前启动帧的压缩。 显示管还可以被配置为确定响应于检测各种条件而选择性地允许回写逻辑操作。 显示管可以压缩帧并将被压缩的帧的大小与阈值进行比较。 如果压缩帧的大小超过阈值，则阻止将压缩帧回写到存储器。 可以对其他条件的检测进一步调节压缩帧的回写。