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104 条记录 (耗时 0.019 秒)

    Multiuser receiving device for use in a CDMA system
    101.
    发明授权
    Multiuser receiving device for use in a CDMA system 失效
    用于CDMA系统的多用户接收设备

    公开(公告)号：US6081516A

    公开(公告)日：2000-06-27

    申请号：US906892

    申请日：1997-08-06

    申请人： Shousei Yoshida ,  Akihisa Ushirokawa

    发明人： Shousei Yoshida ,  Akihisa Ushirokawa

    IPC分类号： H04B1/10 ,  H04B1/707 ,  H04B1/7097 ,  H04B7/08 ,  H04B7/216

    CPC分类号： H04B1/71075 ,  H04B2001/71077

    摘要： In a multiuser receiver for use in a Code Division Multiple Access (CDMA) system to produce first through N-th demodulated signals for N-th users in response to an input signal where N is an integer not smaller than unity, the receiver has first through M-th stages, where M is an integer not smaller than unity. In each stage, first through N-th interference cancellation units are included to form the first through the N-th users. Each interference cancellation unit is supplied with a cancellation error signal obtained from a previous interference cancellation to produce an interference replica signal and a spread signal concerned with a difference between the interference replica signal and a previous interference replica signal. An n-th interference replica signal is successively sent to an n-th user of the following stages to be demodulated Into an n-th demodulated signal which is received by an n-th user where n is an integer between 1 and N, both inclusive.

    摘要翻译： 在用于码分多址（CDMA）系统的多用户接收机中，响应于N是不小于1的整数的输入信号，为第N个用户产生第一至第N解调信号，接收机具有第一 通过第M阶段，其中M是不小于1的整数。 在每个阶段，包括第一至第N干扰消除单元以形成第一到第N个用户。 向每个干扰消除单元提供从先前的干扰消除获得的消除误差信号，以产生干扰复制信号和与干扰复制信号与先前的干扰复制信号之间的差异有关的扩展信号。 第n个干扰复制信号被连续发送到下一级的第n个用户被解调为由第n个用户接收的第n个解调信号，其中n是1和N之间的整数，两者都 包括的。

    Clock recovery circuit with open-loop phase estimator and wideband phase tracking loop
    103.
    发明授权
    Clock recovery circuit with open-loop phase estimator and wideband phase tracking loop 失效
    具有开环相位估计器和宽带相位跟踪环路的时钟恢复电路

    公开(公告)号：US5235622A

    公开(公告)日：1993-08-10

    申请号：US720929

    申请日：1991-06-25

    申请人： Shousei Yoshida

    发明人： Shousei Yoshida

    IPC分类号： H04L7/00 ,  H04L7/02

    CPC分类号： H04L7/007 ,  H04L7/0029

    摘要： In a clock recovery circuit, a received APSK signal is sampled at a frequency N times higher than the transmitted clock in response to a first clock from a local clock source, and quantized into orthogonal digital APSK samples. An envelope of the orthogonal APSK digital samples is detected (3) and phase correlations are detected (5) between the envelope and locally generated orthogonal sinusoidal signals and averaged by a low-pass filter (6). The arctangent between the low-pass filtered orthogonal signals is detected (7) and applied to a subtracter (8). A threshold comparator (9) compares the subtracter output with N successive values. A digital V.C.O. (10) is supplied with an output signal from the comparator (9) to generate a sample clock f.sub.c at a frequency 1/N of the frequency of the first clock f.sub.s for sampling the digital samples from the A/D converter (1). A phase difference is detected by a phase comparator (12) between the second clock f.sub.c and the sample clock f.sub.c, the phase difference being applied to the subtracter (8) in which the difference between it and the arctangent is determined. The V.C.O. (10) controls the timing of the sample clock in response to the first clock f.sub.s in accordance with the output of the threshold comparator (9).

    摘要翻译： 在时钟恢复电路中，响应于来自本地时钟源的第一时钟，接收到的APSK信号以比发送的时钟高出N倍的频率被采样，并被量化为正交的数字APSK采样。 检测正交APSK数字样本的包络（3），并在包络和本地生成的正交正弦信号之间检测相位相关（5），并通过低通滤波器（6）进行平均。 检测低通滤波正交信号之间的反正切（7）并施加到减法器（8）。 阈值比较器（9）将减法器输出与N个连续值进行比较。 数字化V.C.O. （10）被提供有来自比较器（9）的输出信号，以产生第一时钟fs的频率的1 / N的采样时钟fc，以对来自A / D转换器（1）的数字采样进行采样。 相位差由第二时钟fc和采样时钟fc之间的相位比较器（12）检测，相位差被施加到确定其与反正切之间的差值的减法器（8）。 V.C.O. （10）根据阈值比较器（9）的输出，响应于第一时钟fs控制采样时钟的定时。

    Variable bit rate clock recovery circuit
    104.
    发明授权
    Variable bit rate clock recovery circuit 失效
    可变比特率时钟恢复电路

    公开(公告)号：US4891598A

    公开(公告)日：1990-01-02

    申请号：US241669

    申请日：1988-09-08

    申请人： Shousei Yoshida ,  Susumu Otani

    发明人： Shousei Yoshida ,  Susumu Otani

    IPC分类号： H04L7/027 ,  H04L7/00 ,  H04L7/033 ,  H04L27/22

    CPC分类号： H04L7/0334

    摘要： In a variable bit rate clock recovery circuit, a phase difference between an input demodulated signal and a recovered clock signal is detected, the detected phase difference signal is filtered by a loop filter and is then integrated, the integrated signal is supplied as an address to first and second ROMs, which store data of cosine and sine waves in advance, output data from the first and second ROMs are respectively D/A-converted by first and second D/A converters, an output signal from a variable frequency generator is modulated by using an output from the first D/A converter, a signal obtained by shifting the output signal from the variable frequency signal generator by .pi./2 radians is modulated by an output from the second D/A converter, and the respective modulated signals are synthesized, thereby obtaining a reference clock signal.