公开(公告)号：US4251865A

公开(公告)日：1981-02-17

申请号：US968066

申请日：1978-12-08

Applicant: Morris A. Moore ,  Robert H. Bass

Inventor： Morris A. Moore ,  Robert H. Bass

IPC: H04B7/24 ,  G06F13/22 ,  H04Q7/10 ,  H04Q7/20 ,  G06F3/04 ,  H04J6/00 ,  H04Q5/00

CPC classification number: G06F13/22

Abstract: Channel efficiency in a communications link between a controller and multiple portable units is increased by polling the active units and a set number of inactive units in a sequence where a "poll" consists of sending the binary coded address of the portable unit. The stream of transmitted data bits is only interrupted by a response from the portable unit, then resumed at the end of the response or a given portion of the response. During the reception of the response, certain other types of messages can be sent out by the controller. Portable responses can be automatic responses as to status, etc., or can be data initiated by the operator of the portable unit keyboard and stored in the portable unit memory until "armed" by the operator, then automatically transmitted to the controller when the portable unit address is received.

Abstract translation: 在控制器和多个便携式单元之间的通信链路中的信道效率通过轮询有效单元和序列中的一组无效单元来增加，其中“轮询”由发送便携式单元的二进制编码地址组成。 所传输的数据位流仅由便携式单元的响应中断，然后在响应结束或响应的给定部分恢复。 在接收响应期间，控制器可以发送某些其他类型的消息。 便携式响应可以是关于状态等的自动响应，或者可以是由便携式单元键盘的操作者发起并存储在便携式单元存储器中的数据，直到由操作者“挂起”，然后当便携式 接收单位地址。

公开(公告)号：US4186380A

公开(公告)日：1980-01-29

申请号：US844339

申请日：1977-10-21

Applicant: Allan I. Edwin ,  Melvin T. Bennett

Inventor： Allan I. Edwin ,  Melvin T. Bennett

IPC: G06F13/42 ,  H04B1/74 ,  H04L12/437 ,  H04Q5/00

CPC classification number: H04L12/437 ,  G06F13/4213 ,  H04B1/745

Abstract: A communication system for linking a central computer to a plurality of remotely spaced terminals employs a single run of coaxial cable formed in a loop extending in the vicinity of each of the terminals with its two ends terminating adjacent the head-end computer. The output of the computer is provided to a normally operative primary channel transmitter connected to one end of the cable as well as to a normally inoperative, secondary channel transmitter connected to the other end of the cable. Each of the terminals includes receivers for both the primary and secondary channel. Primary channel signal detectors located at the head-end and at each of the terminals energize the secondary channel transmitter and/or the secondary channel receivers at their respective detectors when they fail to receive the primary channel carrier. Failure of the primary channel transmitter or a break in the cable thus causes energization of the secondary transmitter and the secondary channel receivers at those terminals affected by the malfunction. Terminal polling protocols, initiated by the computer, employ both the primary and secondary transmitters to determine the condition of each of the elements of the system.

Abstract translation: 用于将中央计算机连接到多个远程间隔的终端的通信系统采用在每个终端附近延伸的循环中形成的单行同轴电缆，其两端终止于头端计算机。 计算机的输出被提供给连接到电缆的一端的正常操作的主信道发射机以及连接到电缆的另一端的通常不工作的辅助信道发射机。 每个终端包括主要和次要信道的接收机。 位于前端和每个端子处的主信道信号检测器在它们不能接收主信道载波时在它们各自的检测器处激励辅信道发射机和/或次信道接收机。 主通道发射机的故障或电缆中断导致受到故障影响的那些终端的次发射机和次通道接收机通电。 由计算机启动的终端轮询协议同时使用主发射机和次发射机来确定系统中每个元件的状态。

公开(公告)号：US4136263A

公开(公告)日：1979-01-23

申请号：US809422

申请日：1977-06-23

Applicant: Ioan H. Williams

Inventor： Ioan H. Williams

IPC: H04Q3/545 ,  H04J3/12 ,  H04M9/00 ,  H04Q3/58 ,  H04Q5/00 ,  H04Q11/04

CPC classification number: H04Q11/04 ,  H04J3/12 ,  H04M9/005

Abstract: A telephone intercommunications system has speech channels to which the telephone stations of the system can be selectively linked, a plurality of data channels in time-division multiplex to which the telephone stations can be linked for the transmission of data therebetween, common data synchronizing means, and for each telephone station (1) electronic means for generating a cyclically-recurring frame of data channels, (2) electronic means for writing data into a data channel, (3) electronic means for reading data in each data channel, (4) electronic means for recognizing data appertaining to the channel, (5) electronic means for causing the station to be linked to a speech channel identified by a data channel.

公开(公告)号：US4100533A

公开(公告)日：1978-07-11

申请号：US747700

申请日：1976-12-06

Applicant: Orlando Napolitano ,  Robert Edward Reid ,  Burton R. Saltzberg ,  Nathan Harold Stochel ,  John Ronald Tingley

Inventor： Orlando Napolitano ,  Robert Edward Reid ,  Burton R. Saltzberg ,  Nathan Harold Stochel ,  John Ronald Tingley

IPC: G06F13/00 ,  G06F15/16 ,  G06F15/177 ,  H04Q9/14 ,  H04Q5/00 ,  H04J3/04

CPC classification number: H04Q9/14

Abstract: A multipoint polling system wherein a multipoint switch selectively connects a plurality of remote terminals to a central station in response to remote terminal addresses transmitted on a signaling path to the multipoint switch. Polling apparatus stores portions of a remote terminal address list provided by the central station and transmits individual ones of the stored remote terminal addresses on to the signaling path. The polling apparatus periodically requests different portions of the remote terminal address list and replaces the stored remote terminal address portion with the requested remote terminal address portion.The multipoint switch is advantageously comprised of a plurality of sections with each section of the switch responsive to a portion of the address list for establishing a signaling path between the central station and selected ones of the remote terminals defined by the address list portions. The failure of a multipoint switch section to respond to remote terminal addresses results in the address list portion normally transmitted to the failed section and the address list portion normally transmitted to a remaining active section being transmitted to the active section whereby the active section polls the remote terminals previously polled by both the failed and active sections.

Abstract translation: 一种多点轮询系统，其中响应于在多点交换机的信令路径上发送的远程终端地址，多点交换机有选择地将多个远程终端连接到中心站。 轮询装置存储由中央站提供的远程终端地址列表的部分，并将所存储的远程终端地址中的各个发送到信令路径。 轮询设备周期性地请求远程终端地址列表的不同部分，并用所请求的远程终端地址部分替换存储的远程终端地址部分。

公开(公告)号：US3982061A

公开(公告)日：1976-09-21

申请号：US570688

申请日：1975-04-23

Applicant: Howard Anthony Dorey ,  Robert John Cooke

Inventor： Howard Anthony Dorey ,  Robert John Cooke

IPC: G06F13/42 ,  H04L5/14 ,  H04Q5/00

CPC classification number: G06F13/4213 ,  H04L5/1415

Abstract: In a multi-device data transmission system with source and acceptor devices linked by a data highway and handshake lines, provision is made for automatically adjusting the delay of the handshake cycle to suit the highway length and other determinative factors. This is achieved in that the acceptors do not accept data until told so to do via one handshake line, whereas the source is only allowed to issue this command when it has been told via another handshake line that all acceptors have seen the data. The system determines its own delay in this way and automatically adapts the delay to whatever length of highway is employed, whether a fraction of a meter in a circuit board or several tens of meters in inter-rack wiring.

Abstract translation: 在具有通过数据高速公路和握手线连接的源和接收器的多设备数据传输系统中，提供自动调整握手周期的延迟以适应公路长度和其他确定因素。 这样做是因为接受者在通过一次握手行通知之前不接受数据，而仅当通过另一个握手行通知所有接收者已经看到数据时，才允许该源发出此命令。 该系统以这种方式确定其自身的延迟，并自动将延迟适应于采用的高速公路的任何长度，无论电路板中的电表的几分之一或机架间布线中的几十米。

公开(公告)号：US3975712A

公开(公告)日：1976-08-17

申请号：US550336

申请日：1975-02-18

Applicant: Edward C. Hepworth ,  Rodney J. Means ,  Charles I. Peddle

Inventor： Edward C. Hepworth ,  Rodney J. Means ,  Charles I. Peddle

IPC: H03M7/00 ,  G06F13/00 ,  G06F13/38 ,  G06F15/16 ,  G06F15/177 ,  H04L13/06 ,  H04L25/30 ,  G06F3/00 ,  H04J3/00 ,  H04Q5/00

CPC classification number: G06F13/38

Abstract: An integrated circuit asynchronous communications interface adapter (ACIA) includes circuitry on a semiconductor chip for interfacing with a bidirectional data bus of a microcomputer. Bus interface circuitry on the ACIA chip controls data transfer between the microcomputer data bus and a transmit data register and a read data register on the ACIA chip. Transmitting circuitry on the ACIA chip converts data from a parallel format to a serial format. Receiving circuitry on the ACIA chip accepts data in a serial format and converts it to a parallel format prior to transferring it to a receive data register. A control register controls data transfer throughout the ACIA chip. A status register on the ACIA chip may be interrogated under program control to determine the status of registers and/or correctness of data format, status of interrupt logic or modem control lines. Several Modem and/or peripheral control functions, including a "clear-to-send" input, a "request-to-send" output and a "data-carrier-loss detected" input are provided by circuitry on the ACIA chip.

Abstract translation: 集成电路异步通信接口适配器（ACIA）包括用于与微型计算机的双向数据总线接口的半导体芯片上的电路。 ACIA芯片上的总线接口电路控制微机数据总线与发送数据寄存器之间的数据传输以及ACIA芯片上的读取数据寄存器。 ACIA芯片上的发送电路将数据从并行格式转换为串行格式。 ACIA芯片上的接收电路以串行格式接收数据，并将其转换为并行格式，然后将其传输到接收数据寄存器。 控制寄存器控制整个ACIA芯片的数据传输。 可以在程序控制下询问ACIA芯片上的状态寄存器，以确定寄存器的状态和/或数据格式的正确性，中断逻辑或调制解调器控制线的状态。 包括“清除发送”输入，“请求发送”输出和“数据载波丢失检测”输入的多个调制解调器和/或外设控制功能由ACIA芯片上的电路提供。

公开(公告)号：US3947819A

公开(公告)日：1976-03-30

申请号：US537724

申请日：1974-12-31

Applicant: William R. Wells

Inventor： William R. Wells

IPC: H04Q5/00

CPC classification number: G05B19/0423 ,  H04Q2213/1332 ,  H04Q2213/13322

Abstract: A plurality of channel expander devices is operated in response to the channel outputs of a programmer. Means are provided for detecting information in the output channels of the programmer. The programmer output channel information is stored in a first storage means. The channel expander devices are energized one at a time in response to the stored information. A reset signal is generated in response to predetermined information in the programmer output channels, and the first storage means are reset in response to the reset signal.

Abstract translation: 响应于编程器的通道输出操作多个通道扩展器设备。 提供用于检测编程器的输出通道中的信息的装置。 编程器输出通道信息存储在第一存储装置中。 响应于所存储的信息，频道扩展器装置一次一个地被通电。 响应于编程器输出通道中的预定信息产生复位信号，并且响应于复位信号复位第一存储装置。

公开(公告)号：US3914743A

公开(公告)日：1975-10-21

申请号：US30920772

申请日：1972-11-24

Applicant: BELL TELEPHONE LABOR INC

Inventor： FITCH SCOTT MCDOWELL ,  KOLENSKY LEO MICHAEL ,  PANEK JOSEPH CONRAD ,  RIFE DAVID CHARLES ,  SCHAEFER WALTER RUDOLPH

IPC: H04L12/00 ,  H04Q5/00

CPC classification number: H04L12/00

Abstract: A multipoint hub or junction unit has a main channel connected to a control station of a selective calling line and a plurality of branch lines, certain of the branch lines connected to downstream line stations and one branch line connected to a main channel of a downstream multipoint junction unit whose branches are connected to other line stations. Normally, downstream data signals from the control station are split by the hub and broadcast to all the branches, the signals to the downstream hub being split again. Upstream transmission on each branch is combined and propagates to the main line. The multipoint junction unit normally blocks upstream supervisory signals. When branch lines are to be tested, signaling equipment is connected into the main line and signals the hub to block all its branches, to select blocked branches to be tested and to unblock the selected branches to permit passage of upstream and downstream data and supervisory signals.

Abstract translation: 多点集线器或连接单元具有连接到选呼线路和多条分支线路的控制站的主通道，连接到下游线路站的某些分支线路和连接到下游多点的主通道的一条分支线路 分支连接到其他线路站的接线单元。 通常，来自控制站的下行数据信号由集线器分割并广播到所有分支，到下游集线器的信号再次被分离。 每个分支上的上行传输被组合并传播到主线。 多点连接单元通常阻止上行监控信号。 当要测试分支线路时，信号设备连接到主线路，并向集线器发出信号以阻止其所有分支，选择被阻止的分支，以解锁所选择的分支以允许上下游数据和监控信号通过 。

公开(公告)号：US3905020A

公开(公告)日：1975-09-09

申请号：US43956774

申请日：1974-02-04

Applicant: WAYNE ELECTRONIC PRODUCTS CO

Inventor： KNOX MARION D

IPC: H04M19/02 ,  H04Q5/00

CPC classification number: H04M19/02

Abstract: A solid state programmable switch apparatus for producing random and sequential output pulses for control applications. The apparatus consists of timing circuitry for providing either monostable or astable trigger output to sequentially drive a decimal counter device. Buffer circuitry provides high voltage decimal inputs to randomly drive the decimal counter and to enterface output pulses to each of a plurality of respective inputs to a programmable memory module. The memory module is programmable through pin plug interconnection to provide the desired output as desired to a plurality of respective output amplifier and control circuits.

Abstract translation: 一种用于产生用于控制应用的随机和顺序输出脉冲的固态可编程开关装置。 该装置包括用于提供单稳态或不稳定触发输出以顺序驱动十进制计数器装置的定时电路。 缓冲电路提供高电压十进制输入，以随机驱动十进制计数器，并将输入脉冲输入到可编程存储器模块的多个相应输入中的每一个。 存储器模块可通过针插头互连来编程，以根据需要向多个相应的输出放大器和控制电路提供期望的输出。

公开(公告)号：US3846756A

公开(公告)日：1974-11-05

申请号：US37334573

申请日：1973-06-25

Applicant: WESTINGHOUSE ELECTRIC CORP

Inventor： SCHMITZ L

IPC: G06F7/00 ,  E05B49/00 ,  G06F7/02 ,  G06F17/30 ,  G07C9/00 ,  G08B25/00 ,  G08B25/04 ,  H03K19/177 ,  H04Q5/00

CPC classification number: G07C9/0069 ,  G06F7/02

Abstract: The modification of a programmable read only memory circuit. One or more of the outputs are supplied as feedback signals to corresponding inputs transforms the conventional read only memory circuit into a circuit capable of memory and sequential logic functions.

Abstract translation: 修改可编程只读存储器电路。 将一个或多个输出作为反馈信号提供给相应的输入，将传统的只读存储器电路转换成能够存储和顺序逻辑功能的电路。