公开(公告)号：US20010052619A1

公开(公告)日：2001-12-20

申请号：US08548545

申请日：1995-10-26

Inventor： SHUNSUKE INOUE ,  MAMORU MIYAWAKI ,  TETSUNOBU KOCHI

IPC: H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC classification number: H01L27/1203 ,  H01L27/1211 ,  H01L29/785

Abstract: In a semiconductor device which has capacitors means respectively connected to multiple input terminals, and in which the remaining terminals of the capacitors are commonly connected to a sense amplifier, the capacitors and the sense amplifier are formed by utilizing a semiconductor layer on an insulating surface, whereby high-speed, high-precision processing of signals having a large number of bits supplied from the multiple input terminals is realized by a small circuit scale.

Abstract translation: 在具有分别连接到多个输入端子的电容器装置并且其中电容器的其余端子共同连接到读出放大器的半导体器件中，通过在绝缘表面上利用半导体层形成电容器和读出放大器， 从而通过小的电路规模实现从多个输入端子提供的具有大量位的信号的高速，高精度处理。

公开(公告)号：US20010045604A1

公开(公告)日：2001-11-29

申请号：US09824225

申请日：2001-04-03

Applicant: Hitachi, Ltd.

Inventor： Katsuya Oda ,  Katsuyoshi Washio

IPC: H01L029/76 ,  H01L027/12

CPC classification number: B82Y10/00 ,  H01L21/823807 ,  H01L21/8249 ,  H01L27/0623 ,  H01L27/0922 ,  H01L29/66439 ,  H01L29/7378 ,  H01L29/7782

Abstract: A semiconductor device having an MODFET and at least one other device formed on one identical semiconductor substrate, in which an intrinsic region for the MODFET is formed by selective growth in a groove formed on a semiconductor substrate having an insulation film on the side wall of the groove, and single-crystal silicon at the bottom of the groove, is disclosed. The step between the MODFET and the at least one other device mounted together on one identical substrate can be thereby decreased, and each of the devices can be reduced in the size and integrated to a high degree, and the interconnection length can be shortened to reduce power consumption.

Abstract translation: 一种具有MODFET和至少一个其它器件的半导体器件，其形成在一个相同的半导体衬底上，其中用于MODFET的本征区域通过在形成于半导体衬底上的沟槽中的选择性生长形成，该半导体衬底上具有绝缘膜 凹槽和沟槽底部的单晶硅。 因此，可以减少在一个相同的基板上安装在一起的MODFET与至少一个其他装置之间的台阶，并且可以将各个装置的尺寸减小到高度集成，并且可以缩短互连长度以减少 能量消耗。

公开(公告)号：US20010045602A1

公开(公告)日：2001-11-29

申请号：US09265697

申请日：1999-03-10

Inventor： SHIGENOBU MAEDA ,  SHIGETO MAEGAWA

IPC: H01L021/00 ,  H01L027/12 ,  H01L031/0392

CPC classification number: H01L29/78615 ,  H01L27/1203 ,  H01L29/458 ,  H01L29/78621

Abstract: An SOI layer is formed so thick that a body region is not fully depleted under conditions of floating and a zero potential. When a MOSFET operates, a negative body potential is applied to the body region through a body electrode. Thus, the body region is fully depleted. The MOSFET is formed equivalently to a conventional MOSFET of a PD mode as to the thickness of the SOI layer, and is equivalent to a MOSFET of an FD mode as to its operation. Therefore, both of advantages of a PD mode MOSFET such as low resistance in source/drain regions, easiness in formation of a contact hole for a main electrode and stability of a silicide layer and an advantage of an FD mode MOSFET such as excellent switching characteristics are compatibly implemented.

Abstract translation: SOI层形成得很厚，使得在浮动和零电位的条件下，体区域未完全耗尽。 当MOSFET工作时，通过体电极将负电位施加到身体区域。 因此，身体区域完全耗尽。 MOSFET等效于PD模式的常规MOSFET关于SOI层的厚度，并且相当于FD模式的MOSFET的操作。 因此，源极/漏极区域中的低电阻，容易形成主电极的接触孔和硅化物层的稳定性等PD模式MOSFET的优点以及诸如优异的开关特性的FD模式MOSFET的优点 兼容实施。

公开(公告)号：US20010017372A1

公开(公告)日：2001-08-30

申请号：US09791182

申请日：2001-02-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Jun Koyama

IPC: H01L021/00 ,  H01L021/84 ,  H01L027/12

CPC classification number: H01L51/5253 ,  G02F1/136286 ,  G09G3/3233 ,  G09G3/3266 ,  G09G3/3291 ,  G09G3/3648 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/027 ,  H01L27/1222 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/3211 ,  H01L27/3248 ,  H01L27/3276 ,  H01L27/3279 ,  H01L51/0097 ,  H01L51/524 ,  H01L2251/301 ,  H01L2251/5338 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder 100 and a buffer section 101. The decoder 100 includes a plurality of NAND circuits each including p-channel TFTs 104 to 106 connected to each other in parallel and other p-channel TFTs 107 to 109 connected to each other in series. The buffer section 101 includes a plurality of buffers each including three p-channel TFTs 114 to 116.

Abstract translation: 可以提供廉价的显示装置，以及使用该装置的电气设备。 在像素部分和驱动电路被包含在同一绝缘表面上的显示装置中，驱动电路包括解码器100和缓冲器部分101.解码器100包括多个NAND电路，每个NAND电路包括p沟道 并联连接的TFT104〜106，以及串联连接的其他p沟道TFT107〜109。 缓冲器部分101包括多个缓冲器，每个缓冲器包括三个p沟道TFT 114至116。

公开(公告)号：US20010015462A1

公开(公告)日：2001-08-23

申请号：US09734771

申请日：2000-12-12

Applicant: U.S. Philips Corporation

Inventor： Martin J. Powell

IPC: H01L021/00 ,  H01L021/84 ,  H01L027/01 ,  H01L027/12

CPC classification number: H01L29/66757 ,  H01L21/28158 ,  H01L29/4908 ,  H01L29/66765

Abstract: A method of manufacturing a thin film transistor (TFT) is disclosed comprising source and drain electrodes joined by a semiconductor channel layer, a gate insulating layer formed from at least two sublayers and a gate electrode. The method comprising the steps of forming the gate insulating layer by depositing a thin film sublayer using a thin film technique; and depositing a printed sublayer by printing, wherein the thin film sublayer is located adjacent the semiconductor channel layer. The TFT may be a top gate TFT wherein the thin film sublayer is formed on the semiconductor channel layer, and wherein the printed sublayer is formed over the thin film sublayer. Alternatively, the TFT may be a bottom gate TFT wherein the printed sublayer is formed over the gate electrode; wherein the thin film sublayer is formed over the printed sublayer, and wherein the semiconductor channel layer is formed on the thin film sublayer.

Abstract translation: 公开了一种制造薄膜晶体管（TFT）的方法，其包括由半导体沟道层连接的源电极和漏电极，由至少两个子层和栅电极形成的栅极绝缘层。 该方法包括以下步骤：通过使用薄膜技术沉积薄膜子层来形成栅极绝缘层; 以及通过印刷沉积印刷的子层，其中所述薄膜子层位于所述半导体沟道层附近。 TFT可以是顶栅TFT，其中薄膜子层形成在半导体沟道层上，并且其中印刷的子层形成在薄膜子层上。 或者，TFT可以是底栅TFT，其中印刷的子层形成在栅电极上; 其中所述薄膜子层形成在所述印刷的子层上，并且其中所述半导体沟道层形成在所述薄膜子层上。

公开(公告)号：US20010007367A1

公开(公告)日：2001-07-12

申请号：US09756412

申请日：2001-01-08

Inventor： Yasunori Ohkubo

IPC: H01L027/12 ,  H01L021/00 ,  H01L021/84

CPC classification number: H01L21/76264 ,  H01L21/76254 ,  H01L21/76275 ,  H01L21/76283

Abstract: A semiconductor substrate, for forming a circuit pattern of a semiconductor chip, comprised of a substrate, an insulating film formed on the substrate, and a semiconductor layer formed on the insulating film, wherein the semiconductor layer is isolated by the insulating film for every region formed with a circuit pattern of a semiconductor chip, able to be generally used even if a silicon on insulator or semiconductor on insulator (SOI) layer is isolated by an insulating film, and a process of production of an SOI substrate, enabling a reduction of thickness of the SOI layer and able to suppress the manufacturing costs and variation in the thickness of the SOI layer, comprising forming a groove in a first substrate made of a semiconductor, forming a first insulating film in the groove and on the first substrate, injecting hydrogen ions to form a peeling layer, bonding a second substrate, peeling off the first substrate by heat treatment while leaving the semiconductor layer, and polishing the semiconductor layer by chemical mechanical polishing or the like using the surface of the first insulating film projecting out at a bottom of the groove as a stopper.

Abstract translation: 一种用于形成半导体芯片的电路图案的半导体衬底，由衬底，形成在衬底上的绝缘膜和形成在绝缘膜上的半导体层组成，其中半导体层通过每个区域的绝缘膜隔离 形成有半导体芯片的电路图案，即使通过绝缘膜隔离绝缘体上的绝缘体或绝缘体上的绝缘体（SOI）层，也能够通常使用SOI基板的制造工序，能够减少 SOI层的厚度，能够抑制SOI层的制造成本和厚度的变化，包括在由半导体构成的第一基板中形成槽，在槽内和第一基板上形成第一绝缘膜，在第一基板上注入 氢离子形成剥离层，接合第二基板，通过在离开半导体层的同时通过热处理剥离第一基板，并抛光 通过化学机械抛光等使用在凹槽的底部突出的作为止动件的第一绝缘膜的表面进行半导体层的加工。

公开(公告)号：US20010000921A1

公开(公告)日：2001-05-10

申请号：US09751163

申请日：2000-12-29

Applicant: International Business Machines Corporation

Inventor： Salvatore N. Storino ,  Andrew Douglas Davies

IPC: H03K019/096 ,  H01L027/12 ,  H01L027/01 ,  H01L031/0392

CPC classification number: H01L27/0266

Abstract: The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Abstract translation: 本发明是一种用于消除绝缘体上硅（SOI）金属氧化物半导体（MOS）器件中的寄生双极晶体管作用的装置和方法。 根据本发明，提供耦合到所述SOI电子器件的SOI电子器件和有源放电器件以去激活寄生双极晶体管。 通过控制有源放电装置的导通来使寄生双极晶体管的动作失效，所述有源放电装置耦合到所述SOI装置。

公开(公告)号：US20010000627A1

公开(公告)日：2001-05-03

申请号：US09736139

申请日：2000-12-13

Applicant: Semiconductor Energy Laboratory Co., Ltd

Inventor： Masahiko Hayakawa ,  Yosuke Tsukamoto

IPC: H01L021/00 ,  H01L031/0392 ,  H01L029/04 ,  H01L027/12 ,  H01L031/036 ,  H01L027/01 ,  H01L031/0376 ,  H01L031/20 ,  H01L021/84

CPC classification number: H01L29/78696 ,  G02F1/1368 ,  H01L27/12 ,  H01L29/42384

Abstract: In a thin-film transistor of multi-gate structure, the width of a channel forming region 108 closest to a drain region 102 is made the narrowest. This prevents a transistor structure closest to the drain region from first deteriorating. Further, the channel length at the vicinity of a center of an active layer is intentionally widened, so that the amount of current flowing through the vicinity of the center of the active layer is decreased and the deteriorating phenomenon due to heat accumulation is prevented. Therefore, a semiconductor device with a high reliability is realized.

公开(公告)号：US20040217423A1

公开(公告)日：2004-11-04

申请号：US10833050

申请日：2004-04-28

Inventor： Jong-Wan Park ,  Jea-Gun Park

IPC: H01L027/12

CPC classification number: H01L21/76254 ,  H01L27/1214 ,  H01L27/1266 ,  H01L29/78603 ,  H01L31/18

Abstract: The present invention relates to a flexible single-crystal film and a method of manufacturing the same from a single-crystal wafer. That is, the present invention can manufacture a silicon-on-insulator (SOI) wafer comprising a base wafer, one or more buried insulator layers, and a single-crystal layer into a flexible single-crystal film with a desired thickness by employing various wafer thinning techniques. The method for manufacturing a flexible film comprises the steps of (i) providing a SOI wafer comprising a base wafer, one or more buried insulator layers on the base wafer, and a single-crystal layer on said one or more buried insulator layers, (ii) forming one or more protective insulator layers on said single-crystal layer, (iii) removing said base wafer, and (iv) removing one or more of the insulator layers.

公开(公告)号：US20040207015A1

公开(公告)日：2004-10-21

申请号：US10798574

申请日：2004-03-12

Inventor： Hoon Kim

IPC: H01L021/00 ,  H01L027/12

CPC classification number: H01L29/66757 ,  H01L29/42384 ,  H01L29/78603

Abstract: The present invention relates to a thin film transistor for preventing short of circuit by step and a method for fabricating the thin film transistor and provides a thin film transistor including a buffer layer formed on glass substrate; an activation layer formed on the buffer layer; and a gate insulation layer formed on the buffer layer including the activation layer, with the buffer layer having a step formed between a lower part of the activation layer and a part except the lower part of the activation layer.

Abstract translation: 薄膜晶体管技术领域本发明涉及一种用于防止电路不通的薄膜晶体管和薄膜晶体管的制造方法，并且提供了一种薄膜晶体管，其包括形成在玻璃基板上的缓冲层; 形成在缓冲层上的活化层; 以及形成在包括活化层的缓冲层上的栅极绝缘层，其中缓冲层具有在活化层的下部和除了活化层的下部之外的部分之间形成的台阶。